51 Research and Design, Electronic Engineers website - Embedded Systems, MCU, DSP, EDA, Test and Measurement, Components, Communications, Power, Microelectronics, Semiconductors

 1. Way choice Starts modelsim the se simulation tool, chooses in the main window[file]-

The N odd number frequency division, must make the dutyfactor is 50%, realizes by the following mentality:A, by an original clock cycle N time of achievement processing period; (function which counts with counter)B, the production dutyfactor is N2:　N2 1 (division takes entire) profile; (by counter value sampling)C, B production profile phase-shift original clock's a half cycle; (with negative along function which hits)D, if the high level occupies the N2 width, outputs B and the C profile or; If the ...

1. hardware design basic principle Speed and area balanced and principal of reciprocity: If a design the succession remainder is big, can run the frequency is higher than the design requirements far, can be possible to reduce the entire design consumption through the module multiplying the chip area, this is trades the area with the speed advantage to save; Otherwise, if a design's succession request is very high, the ordinary method cannot achieve the design ...

The modernized production and the scientific research enhance day by day to the image gathering system's request. The traditional image gathering card speed is slow, the processing function is simple, cannot satisfy the special request well, therefore, we have constructed the high speed image gathering system. It mainly includes the image gathering module, the image preliminary processing module as well as the bus interface module and so on. These modules are realize in FPGA using the VHDL programming. The ...

    In recent years, along with the integrated circuit technology's development, carried on the chip or the system design with the traditional method has not been able to satisfy the request, urgent needs to raise the rated capacity. Under such technical background, can reduce the design difficulty the VHDL design method more and more widely to use greatly. But the VHDL design is the behavior level design?? Brings the question is designer's design ponder and circuit structure comes apart. ...

Introduction 　　Along with computer and microelectronic technology development, electronic design automation EDA (Electronic Design Automation) and programmable logical component PLD (Programmable Logic Device) the development is rapid, uses the EDA software to carry on PLD skilled the component development to become the basic skill which electronic engineer must grasp. The advanced EDA tool already from the traditional design method change from bottom to top for the design method from the top, (Hardware Description Language) described the system-level ...

TESTBENCH grammar reference always module clock_gen; reg clock; //Initialize clock at time zeroinitialclock = 1 ' b0; //Toggle clock every half cycle (time period = 20)always#10 clock = ~clock; initial#1000 $finish; endmoduleforever module synchronize; //Example 2: Synchronize two register values at every positive edge of //clockreg clock;reg x, y; initialbeginclock = 1 ' b0;x = 1 ' b0;y = 1 ' b0;#100000 $finish;end always #5 clock = ~clock;always #11 y = ~y; initialforever @ ...

      With together circuit wafer on, because the holding wire the high frequency burr which walks the line to be excessively long produces we may through, in the close input end connects 100 ohm about the resistance to filter. But regarding the board outside the signal, or in the board other disturbances creates time the big vibration has to use the integrated circuit to come the filter, namely strings together a resistance also to want and a capacity ground. ...

     This article take ModelSim the SE 5.6 editions as a foundation, introduces ModelSim SE the most essential usage, profound I cannot.    After you install ModelSim SE, may the beginning way establish yours ModelSim SE as yours job category (for example e:\verilog), the concrete method is clicks on the attribute fence again in the right key one-shot execution document ModelSim SE icon, may see ModelSim SE the beginning position, changes your job category to be possible.    Studies the verilog ...

In uses Verilog HDL compiles logical and so on limited state machine times, state machine's each condition usually by the parameter indicated that, but when uses the ModelSim simulation time, the state machine variable in the wave window by the binary code's form demonstrated that for example: 4 ' h0, 4 ' h1 and so on. This kind of display format is not very direct-viewing, but we may use the order which ModelSim provides the state machine variable by ...