This documents explained in detail the biplate ADSP-21160 system’s load, how as well as integrated development environment the vectoring procedure will upload in VISUAL in the DSP through DSP to FLASH. The SHARC series is the American Simulation Component Company (ANALOG DEVICES) one of important chip series. This serial products has the very strong digital signal processing ability, many piece of SHARC chips may constitute the handling ability formidable system, widely applies in the correspondence, domains and so on radar. The SHARC series chip race has contained ADSP-21060/21061/21601/21065L, as well as newest 21160/21161 series. Not only their common feature has the formidable handling ability, and has the rich connection resources, very suits a many piece of cascade constitution function more complex system.
In many piece of systems, how carries on the program load to many piece of SHARC DSP is a quite real issue, this article is carries on the analysis from the hardware skeleton and in the software flow to the biplate ADSP-21160 SHARC system’s load question.
1. Biplate ADSP-21160 system’s hardware skeleton
1.1 biplate ADSP-21160 connection Take AD21160N as the example.
Two piece of SHARC respectively is DSP1 and DSP2, the corresponding ID2~0 base pin sets is 001 and 010. And what ID is 001 is the main piece, what ID is 010 is from the piece.
If the system uses the non-main engine guidance pattern, each piece’s /HBG,/HBR sets separately for the invalid condition (pulls high).
If loads uses the EPROM guidance, after each piece of SHARC /BMS makes the line or, and EPROM /CE is connected. And each piece’s BR1, BR2 corresponds connected, other BRx set invalid to (pulls high).
The ACK signal had decided the main line power’s shift, should pull high the ACK compulsion. When ID = 000 (monolithic system), or ID = 001 (many piece of systematic main pieces) time, the ACK automatic interior will pull high. In order to order to insure, may pulls the main piece and from piece ACK in the exterior compulsion high. Otherwise, will present the main line power not to be able to give from the piece phenomenon.
The address bus and the data bus correspondence is connected, and with the EPROM address wire, the data line is connected.
After the biplate system adds the electricity, main piece ADSP-21160 and is reads out 256 bytes from piece ADSP-21160 from EPROM the initial segments. These 256 byte’s segment has contained the load initialization information, has a skipping table finally in this section, has demonstrated the different ID procedure correspondence different memory address. SHARC through reads own system register to obtain own ID, then takes out the procedure code offset address which one must load.
According to the SHARC main line sanction mechanism, ID number low SHARC has the high priority, therefore the ID=001 main piece loads first. After the first piece of load finished, informed the second piece through BR1 to be possible to start to load, the main line power shifted to ID=010 SHARC. After the second piece of load finished, through the BR2 notice system, then this biplate system started the operating procedure.
1.2 ADSP-21160 and FLASH connections
FLASH CE, OE, We are separately connected with AD21160 BMS, RD, WR, the BMS expression selects patches or strips of land as worth saving for seed the signal, WR is writes a letter the number, RD is reads the signal. Moreover the FLASH address wire and the data line also separately connect with DSP.
If is connected AD21160 MS0~2 and the FLASH piece route selection, has become FLASH the AD21160 exterior expansion memory block. This will bring conveniently, first, may respectfully receive and read in FLASH straight in VisualDSP for SHARC the data, will not need to program the read-out; Next, may use the direct read-write the means fever to write FLASH, but may also use the software control insertion the standby period.
If only uses BMS and FLASH is connected, then can only use DMA the way to carry on FLASH the read-write operation.
1.3 fever write FLASH the way
When uses BMS selects patches or strips of land as worth saving for seed FLASH time, FLASH takes AD21160 the byte storage space, AD21160 can only through the DMA way visit FLASH.
Completes a DMA transmission to carry on the establishment to 4 memory reflection register. The attention, writes FLASH only to be able to use DMA10.
Specifically as follows:
1. establishes BSO, causes BMS to force effectively, and opens DMA10 the interrupt to enable;
USTAT1 = DM(SYSCON);
BIT SET USTAT1 BSO;
DM(SYSCON) = USTAT1;
BIT SET MODE1 IRPTEN;
BIT SET IMASK EP1I;
BIT SET IMASK EP0I;
2. the attention to FLASH writing is the byte programming, must therefore the data file transformation be the 8bit byte form. Each time DMA can only send out a byte.
3. because BMS selects patches or strips of land as worth saving for seed FLASH, therefore cannot carry on the insertion waiting status to the FLASH read-write the instruction. Is accommodating the means are, the DMA number of times register supposes is 3 or 3 above integers, namely reads in the identical byte many times continuously to the identical address, equivalent in insertion waiting status, pulls the width to write enables the signal the width.
4. the related FLASH read-write succession, please refer to FLASH datasheet which uses, and defers to its succession and the control word request, uses SHARC the assembly directive to compile FLASH the fever to write the procedure. This procedure may move through the simulator on the SHARC chip, realizes writes the .dat document fever in FLASH.
2. Biplate system’s LDF document
The LDF document is carries on the explanation and the definition document to system’s memory resources, biplate system’s LDF and monolithic LDF differs from. For better carries on between the biplate the correspondence, its LDF document general definition is as follows:
ARCHITECTURE(ADSP-21160) 21160 systems
SEARCH_DIR ($ADI_DSP \ 211xx \ lib) storehouse document way
$LIBRARIES = lib160.dlb;
COMMAND_LINE_OBJECTS.
$OBJECTS = COMMAND_LINE_OBJECTS;
MEMORY // internal memory block definition
{mem_rth {TYPE (PM RAM) START(0×00040000) END(0×000400ff) WIDTH(48)} // procedure memory, interrupts to the meter section
mem_pmco {TYPE (PM RAM) START(0×00040100) END(0×000491ff) WIDTH(48)} // procedure memory, code section
mem_pmda {TYPE (PM RAM) START(0×0004db00) END(0×0004efff) WIDTH(32)} // procedure memory, data segment
mem_dmda {TYPE (DM RAM) START(0×00050000) END(0×00057fff) WIDTH(32)} // data memory, data segment
mem_dmex {TYPE (DM RAM) START(0×00800000) END(0×00800fff) WIDTH(32)} // data memory block, outside piece data segment
}
below // is to many pieces (ID1 and ID2) the mapping space explanation
MPMEMORY
{ID1 {START(0×00100000)} the // first piece maps 0×00100000
ID2 {START(0×00200000)} the // first piece maps 0×00200000
}
Next is to the sharing exterior memory block statement, for instance component’s and so on external the SRAM storage spaces
{OUTPUT (shared.sm)
SECTIONS
{dxe_dmex
{INPUT_SECTIONS (shared.doj(sram_da))
} >mem_dmex
}
}
PROCESSOR ID1 // processor ID1 section definition.
{ LINK_AGAINST (ID2.dxe)
OUTPUT (ID1.dxe)
SECTIONS
{dxe_rth
{INPUT_SECTIONS (ID1.doj(seg_rth) $LIBRARIES(seg_rth))
} >mem_rth
dxe_pmco
{INPUT_SECTIONS (ID1.doj(seg_pmco) $LIBRARIES(seg_pmco))
} >mem_pmco
dxe_pmda
{INPUT_SECTIONS (ID1.doj(seg_pmda) $LIBRARIES(seg_pmda))
} >mem_pmda
dxe_dmda
{INPUT_SECTIONS (ID1.doj(seg_dmda) $LIBRARIES(seg_dmda))
} >mem_dmda
}
}
PROCESSOR ID2 // processor ID2 section definition
{
LINK_AGAINST (ID1.dxe)
OUTPUT (ID2.dxe)
SECTIONS
{dxe_rth
{INPUT_SECTIONS (ID2.doj(seg_rth) $LIBRARIES(seg_rth))
} >mem_rth
dxe_pmco
{INPUT_SECTIONS (ID2.doj(seg_pmco) $LIBRARIES(seg_pmco))
} >mem_pmco
dxe_pmda
{INPUT_SECTIONS (ID2.doj(seg_pmda) $LIBRARIES(seg_pmda))
} >mem_pmda
dxe_dmda
{INPUT_SECTIONS (ID2.doj(seg_dmda) $LIBRARIES(seg_dmda))
} >mem_dmda
}
}
Through the above definition, realized stated two piece of AD21160 storage spaces in a LDF document, as well as many stretch of memory block mappings (MMS), with sharing piece external storage area.
3. The fever writes biplate SHARC the flow example
The newly built project, uses the above LDF document statement.
Then compiles two .asm documents: ID1.asm, ID2.asm.
These two .asm document has the independence interrupt to approach the meter, may carry out the respective procedure independently.
For example, may let FLAG0 and the FLAG1 output opposition square-wave in ID1.asm, lets FLAG2 and FLAG3 in ID2.asm outputs another frequency the opposition square-wave.
Translation, might find the new production to be possible execution document ID1.DXE, ID2.DXE.
In VISUAL in the DSP integration environment, the choice project attribute (Project Option), the change is as follows:
1. like the figure above, changes Type by DSP executable file Loader file;
2. like the figure above, designates Multiprocessor, may, in is activated in the choice frame the choice must use .DXE document. In 1, chooses ID1.DXE; In 2, chooses ID2DXE. This means that will load ID1.DXE to the first piece, loads ID2.DXE to the second piece. Kernel file choice default’s 160_prom.dxe, this document is the load nuclear document which provides by AD. Establishes the output filename in Output file (in here is Two_SHARC.ldr); Designates the ASCII form, will produce the 16bit data file; boot type designates eprom, this will produce suits the data file which loads from eprom.
3. after all complete, carries on a translation. Might find the production in the DEBUG folder Two_SHARC.ldr.
4. after meeting the simulator, opens the FLASH fever to write the procedure, wants the agglutination the filename to increase to the procedure. Moves the FLASH agglutination procedure, burnt two piece of loading sequences to FLASH.
5. closes VisualDSP, captures the simulator, starts the goal board, presses down RESET, observes first piece of DSP FLAG0 and FLAG1 through the oscilloscope, with second piece of DSP FLAG2 and FLAG3, inspects whether to have the corresponding opposition square-wave output. If has, explained that biplate AD21160 loads successfully.
4. Concluding remark
American AD Corporation’s SHARC the series DSP many piece of level ability is one of continually its characteristics, introduces two piece of system loading plans from this article to be possible to infer that many piece of SHARC the series DSP chip system’s load is also similar. Many piece of systems similarly must pay attention to system’s hardware construction, contains between many piece of DSP chips the connection mode, the bus arbitration mechanism, as well as with FLASH MEMORY between connection. On the software to the .LDF establishment is the key, it has decided between many piece of DSP mutual visit memory district. Many piece of SHARC systems will display this series chip formidable floating point handling ability greatly, in the correspondence, aspects and so on radar will have the significant application.
Author relation: hanwei2004@sohu.com
