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Abstract: Takes the main engine by PC machine, takes the transmission path through the PC ISA main line and the DSP HPI main engine and the mouth connection, realizes inserts in the card to PC machine ISA DSP chip TMS320VC5402 to carry on the real-time online procedure loading. Key word: DSP HPI main engine and mouth ISA main line soft disposition First, introduction At present, along with microelectronic technology’s swift development, in based on the industry observation and in the data acquisition domain’s PC machine board card product, the high speed DSP chip’s use was already more and more popular. In the numerous factory production’s DSP chip the DSP chip application which (the Texas Instruments) produces by American TI Corporation is most common. The same tradition such as monolithic integrated circuit’s procedure loading process compares, the DSP factory provided for the chip have been more, the more nimble procedure loading method. Actually electronic engineer in does design in the DSP system to use that procedure loading method, should regard the product type to have the choice differently. The current many factories produce in the DSP chip integrated the main engine parallel interface, may complete between the main engine and the DSP parallel data exchange using the main engine and the mouth. For example TI Corporation’s TMS320C54X series DSP chip, AD Corporation ADSP21XX series DSP chip and so on. But main engine and mouth while completes the main engine and DSP carries on the data exchange, but also has the procedure loading function mostly. Uses the DSP chip when the PC board card class electronic products, in fact is one kind of host from the pattern application, namely takes PC machine the main engine, the DSP chip takes from machine. By now used the main engine and the mouth completes the procedure through the PC machine system bus the loading to become one kind both the economy to be practical the way which, and facilitates nimbly. Below take TI Corporation’s TMS320VC5402 as the example (below Jian Chengwei VC5402), this article introduced how to complete DSP procedure by the PC ISA main line HPI (main engine parallel interface) to load, and has given the software and hardware development example. Second, hardware design 1.VC5402 HPI procedure loading process The VC5402 interior has 4K×16 bit word ROM, when on after system electricity replacement, if VC5402 MP/MC pin for low, then the VC5402 PC procedure indicator jumps to the address is 0XFF80 ROM place starts to carry out the replacement vector section procedure. This section of procedures are the factory when leaving the plant solidifies good section of procedures, it first carries out the skipping instruction, jumps is 0XF800 place starts to the address to carry out, starts the ROM content from 0XF800 to be called the procedure loading bin (Bootloader). Was going to judge the user actually in there DSP to select that procedure loading method, but judged whether there was the basis through such as the interrupt, data or in the I/O space fast address unit the specific symbol character whether there is and so on factories already defined the good way to distinguish. It is noteworthy that the VC5402 HPI loading way and C54X series’s other models have the difference slightly. It has the following two points differently: ⑴ The VC5402 HPI loading process will be later completes in replacement process (Reset), will not be completes in the replacement process. ⑵ /INT2 flag bit is not judges the HPI loading pattern the only method, in VC5402 the address is the 0X007F RAM unit content is also judges the HPI loading pattern one method. The PC machine ISA main line (later will be called HOST) as the main engine to be possible to load through the HPI mouth the VC5402 procedure to the VC5402 interior double deposits and withdraws in RAM to start to carry out. Figure 1 ISA main line and VC5402 HPI interface circuit 2. the hardware realizes Realizes the ISA main line and the VC5402 HPI hardware interface is quite simple, needs to pay attention a spot is VC5402 and the ISA bus requirements level switch. Because the ISA main line level is 5V the TTL level, but VC5402 is the 3.3V level, therefore both cannot the direct connection. We may use PHILIPS Corporation’s 74LVC245 level switch chip, this kind of chip uses the 3.3V power supply, can permit 5V and the 3.3V two kind of level input signals. The output is the 3.3V level, may with the 3.3V component direct connection. The electric circuit schematic diagram sees Figure one: Because needs PC to carry on the real-time procedure loading to VC5402, then the VC5402 replacement cannot use the simple RC electric circuit to complete, here uses piece of 74HC74 the D trigger to complete VC5402 by the PC control the replacement process. In the chart, we /HINT and /INT2 in the same place, are continually because VC5402 when moves Bootloader will output a low level automatically in the /HINT pin, like this will cause VC5402 after the replacement had ended can distinguish the current loading pattern immediately is the HPI pattern, but will neglect to other pattern circulation search. When circuit design needs to pay attention to the VC5402 HPI correlation control pin connection. Regarding the control pin, when uses different HOST, the connection will also differ from. Here needs to understand that the HPI main engine and the mouth work’s succession, the succession chart sees Figure two. In the chart /HCS signal is HPI enables the input signal, when uses HPI, the /HCS signal must earth. /HAS is the HPI address lock saves the input signal, this signal when the address bus and the data bus time sharing multiplying’s processor (e.g. 8031) takes HOST saves the signal as the address lock to use; Regarding the ISA main line, its address wire and the data line are separate, therefore /HAS, so long as meets 3.3V then. /HDS1 and /HDS2 are two data locks save the signal, in fact used one to be possible, but another must meet 3.3V. In this example has used /HDS1, but /HDS2 has met 3.3V. Should point out that when does not use the /HAS signal, /HDS1 and the /HDS2 two input signals also have the address lock to save the function, in theirs drop along the time, the VC5402 HPI lock saves HCNTL0, HCNTL1, HBIL and the HR/W four control input signal value. Through these four signal’s value, VC5402 may determine that the present is carries on the operation to that register, is reads the operation or writes the operation, is carries on the transmission to 16 word length high eight low eight, therefore time circuit design must guarantee when /HDS1 or /HDS2 drop along the above four control signal have the correct logic level, otherwise the entire procedure loading process will be defeated. Figure 2 HPI operation succession chart Because the VC5402 interior is 16 data buses, but its HPI main engine and the mouth are actually a 8 data bus, therefore carries on 16 bit words through HPI and HOST the data exchange to need to divide two times to complete, the HBIL signal pointed out that the present is the first byte second byte. The HR/W input signal points out current HOST the direction of data transfer, because here is only carries on the procedure loading to VC5402, namely HOST only carries on to HPI writes the operation, therefore the HR/W earth. As for HCNTL0, the HCNTL1 two input control signal’s function, here might as well summarizes as follows: HOST when carries on the data exchange through HPI and VC5402, in fact is only visit to the VC5402 three registers carries on, they are HPI control register HPIC, HPI address register HPIA and HPI data register HPID. HOST to these three register’s addressing, is completes through input holding wire HCNTL0 and HCNTL1, concrete process following table one. In the practical application usually is HCNTL0, HCNTL1 receives together with HBIL HOST in the address wire. A Table HPI main engine and mouth allocation
In the electric circuit completes PC with piece of GAL16V8 the I/O address decoding. Below comes to VC5402 to carry on the I/O resource distribution. The assignment situation sees Table two. According to the resource distribution, comparison shown in Figure one electricity schematic diagram, writes GAL16V8 the decoding equation of state: IO4=A9*/A8*/A7*/A6*A5*A4*/A3*/A2*/A1*/A0*AEN*/IOW; To VC5402 replacement decoding /IO1 =/IOW ; Delivers /HDS1 to carry on the data lock to save /IO6 =A9*/A8*/A7*/A6*A5*A4*A3*AEN ; HPI address strobe In order to prevent time the 74LVC245 high-resistance output not to stabilize to /HDS1 creates the misoperation, the use 10KΩ resistance carries on to /HDS1 on pulls is necessary. Table two PC to the VC5402 I/O resource distribution
Third, software design 1. software development step Realizes based on the ISA main line to the VC5402 soft disposition, software’s key lies in the HOST side software’s compilation, as for VC5402 operating procedure compilation certainly not at discussion’s category. The HOST side software must complete the duty is assigns the VC5402 operating procedure according to the programmer the good address to carry on beforehand the localization loading then movement. Actually then should load what form document to VC5402, also how to load? In view of this, may summarize the HOST side software with the following four steps: ⑴Production * .OUT form public object file (COFF). when TI Corporation’s C54X integrated development environment CCS 5000 carries on the C54X series the procedure development, can undergo the translation, the link finally produces the *.OUT document. ⑵Carries on the extraction to the *.OUT document, screens to loads the useful code and the address message finally. The first step institute produces because the *.OUT document is the COFF form document, also after is one kind of modular process Bootload, may carry out the document, it may locate the characteristic to cause the user again to be possible to arrange nimbly to the procedure in the permission address range. Because of this, the *.OUT document is not one complete may carry out the code, inside it the package includes some about the procedure in each section such as the start address, section length such auxiliary information, if loads these information together with the procedure code in DSP, the procedure normally will not be carried out. By must probably carry on the auxiliary information to *.OUT with to be possible to carry out the code extraction and to separate. Completes this task is completes depending on the special procedure, is TI Corporation provides, the procedure name is: Coff_both.exe. This procedure may in the TI website the free download, the space be 120K. Carries on the operation using this procedure to the *.OUT document to produce the *.OUT.C document which finally the third step institute needs. ⑶The start address which and the procedure code provides according to the document loads after the extraction *.OUT.C document through HPI to VC5402. Second step produces the *.OUT.C document told the procedure to have several sections explicitly, each section’s size, the section start address as well as each section 16 entered the system code. Had this document, had known should write any content to go to VC5402 in only then to be able to start to carry out the VC5402 procedure. Then must do is through compiles own application procedure 16 to enter the *.OUT.C document in the system code to read in through HPI in VC5402. ⑷Reads in the VC5402 dummy home address program execution’s first address is in the 0X007F unit. After loads all codes finished, finally must in VC5402 in the internal 0X007F RAM unit read in the program execution the first address. When VC5402 examines in the 0X007F unit the value for the non-0 values, knew that the HPI loading process already ended, and the address which assigns from the 0X007F unit starts the executive routine, hence the entire loading process ended. 2. software development example A union chart hardware circuit, compares software development each step, we have given a simple software development example, intends to the reader who causes to be interested regarding this to be able through this example, understood truly carries on the VC5402 loading with HPI the entire process. A Figure VC5402 XF output pin has met a light emitter diode, the VC5402 procedure function causes the twinkle which this diode does not stop. Below carries on according to above four step flow: ⑴Compiles example.asm and the example.cmd document, produces the example.out document with the CCS 5000 integration development software. About through controls the XF pin to cause the light emitter diode twinkle the VC5402 procedure compilation, here no longer gives unnecessary detail. ⑵Places under the identical table of contents Coff_both.exe and the example.out document, enters under the DOS order prompt symbol: Coff_both - out example.out. Will produce by now the example.out.c form the document. This document’s form sees Figure three. This procedure only then section of procedures, namely the .text section, ⑶Writes about in VC5402 the example.out.c document’s in code by HPI internal RAM. The HOST main engine software, needs user to compile, may use VC or the VB transfer driver completes, may also 2.0 complete directly through TURB0 C through the I/O operation, even the available MASM assembly language compiles, the procedure primary mission is reads the example.out.c document and writes the I/O port. The HOST main engine software’s flow chart sees Figure four. Programs the confirmation for ease of the reader, we used TURBO C 2.0 to compile the named HOST_HPI.C mainframe program, the reader have been possible to move this procedure to read the example.out.c document, loaded into VC5402 41 character’s codes. The application method is as follows: Enters under the DOS order prompt symbol: After HOST_HPI.exe, the screen will prompt inputs the example.out.c document the way, for example: Typing: after C:\ti\myprojects\example.out .c, HOST_HPI.exe will complete HOST to load VC5402 the duty, if saw the illumination second-level tube does not stop the twinkle, indicated VC5402 already started the normal operation procedure. Hence, the entire loading process finished. 3. HOST_HPI.C source program /*HOST_HPI.C*/ #include ” stdio.h “ #include ” dos.h “ #define SIZE 100 main() { FILE *fp; Unsigned int DSP_RES, HPIC_H, HPIC_L; Unsigned int HPIA_H, HPIA_L, HPID_H, HPID_L; char *a, ch, filename; unsigned int i, j, length, addr, start[10],*data; printf (”Please input the name file: \ n”); scanf (”%s”, filename); /* input routine filename */ if ((fp=fopen (filename, “r”))==NULL) /* opens program file */ { printf (”cannot open file: \ n”); exit(0); } DSP_RES=0×240; /* establishes DSP various registers’ I/O address */ HPIC_H=0×230; HPIC_L=0×231; HPIA_H=0×234; HPIA_L=0×235; HPID_H=0×236; HPID_L=0×237; outportb(DSP_RES,0×00); the/*DSP replacement (the DSP_RES register sets at 00H) */ delay(2000); the/* time delay guarantees DSP accurate replacement */ outportb(DSP_RES,0×01); /*DSP jumps out the replacement (the DSP_RES register to set at 01H) */ outportb(HPIC_H,0×00); the/*DSP HPIC register sets at 0000H*/ outportb(HPIC_L,0×00); i=0; while (! feof(fp)) whether the/* judgment program file did finish */ { fgets(a, SIZE, fp); fgets(a, SIZE, fp); fscanf (fp, “%s”, a); fscanf (fp, “%s”, a); fscanf (fp, “%x”, &length); /* read data length */ fgets(a, SIZE, fp); fscanf (fp, “%s”, a); fscanf (fp, “%s”, a); fscanf (fp, “%x”, &addr); /* read procedure start address */ fgets(a, SIZE, fp); fgets(a, SIZE, fp); for (j=0; j<length; j ) fscanf (fp, “%x,”, data j); start[i]=addr; the/* save routine starts address */ for (j=0; j<length; j ) /* is DSP data input */ { /* bestows on the address on the program for the DSP HPIA register, bestows on the top digit to bestow on low position */again first outportb(HPIA_H, addr>>8); outportb(HPIA_L, addr&0×00ff); /* bestows on the program data for the DSP HPID register, bestows on the top digit to bestow on low position */again first outportb(HPID_H,*(data j)>>8); outportb(HPID_L,*(data j)&0×00ff); addr ; the/* address on the program adds 1*/ } for (j=0; j<4; j ) fgets(a, SIZE, fp); i ; the/* cycle-index adds 1*/ } fclose(fp); /* closure program file */ outportb(HPIA_H,0×00); /* bestows on 007FH*/for the DSP HPIA register outportb(HPIA_L,0×7f); /* entrusts with DSP procedure start address start [0] HPID register */ outportb(HPID_H, start[0]>>8); outportb(HPID_L, start[0]&0×00ff); printf (”Write data to DSP success! \ n”); the/* returns wrote the data success prompt, the procedure finishes */ } Fourth, conclusion May see through this article, carries on HPI through PC to VC5402 the procedure loading to belong to one kind based on the RAM online programming, compares parallel or serial EEPROM carries on the DSP procedure loading in the use the method, it does not need to the program memory to carry on the fever to write, belongs to one kind of soft disposition. In inserts in the casette test facility performance history based on PC, this method avoided the multiple power failure, the fever writing the procedure inconvenient, enabled the equipment to have the online development characteristic.
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this section of procedures altogether are composed of 41 characters, this segment needs to load to starts the address is in internal RAM which 0X0080 starts moves. But these 41 characters 16 enter the system code is finally truly the VC5402 procedure code which carries out.
