Abstract: With emphasis the introduction take TMS320VC5402 as the core fingerprint recognition system’s hardware design, explained broadly the software design method, gives its hardware debug method finally.
Key word: The DSP fingerprint distinguishes TMS320VC5402
The fingerprint recognition takes the biological features recognition one kind, has its incomparable merit. As a result of may body carrying this kind special “the seal”, therefore is valued more and more person’s. This system uses TI TMS320VC5402 (to hereafter refer to as 5402) takes the core. DSP and the monolithic integrated circuit compare, uses in the algorithm being quite complex, while adds the operand quite big situation. This chip is section of fixed-point DSP, it has reaches as high as 100MIPS the operational capability, simultaneously has the optimized CPU structure and a series of intelligent peripheral device. Below discusses emphatically based on this chip system design.
1 system design
Fingerprint system overall project design as shown in Figure 1.
This system is by fingerprint hardware and so on gathering meter, FPGA, SRAM and Flash is composed. RS232 uses in the data transmission, PC machine may obtain the fingerprint characteristic data through this connection; The Flash memory fingerprint database, LCD use character and DSP procedure; FPGA from takes under the DSP control refers to takes out the chart to put in SRAM; The small keyboard uses in the user inputting the ID number, strengthens this system’s security rating.
1.1 storage space software and hardware design
This system must visit the memory has three:
DSP internal DARAM (the 16K character, uses in depositing constant and variable data space), SRAM and Flash. Because 5402 have 20 address wires to be possible to use for to the procedure space addressing, therefore has the 1M byte addressing space, uses high address wire A19 to differentiate Flash and SRAM. After and SRAM is BootLoader, program run’s space, like this placed Flash the high address to come up. 5402 data addressing space is only 64K, must therefore carry on the paging expansion. In order to avoid with the DARAM access conflict, cannot use a 64K page. Because in 64K low address’s 16K in fact cannot visit, it first low address’s 16K is realized by 64K on cannot visit, it does not have by the DARAM visit, therefore decides as 32K a data page. Assigns a I/O address, then carries on through the I/O address’s decoding to 74LS273 enables the control, finally the lock saves I/O the data to make the data page. When carries on visit to the data space, should divide into the following several steps:
①Analyzes this address, carries on the division. First (low) 15 are in the page the address, latter (high) 6 are the page addresses.
②Whether the judgment page address is 0. If is 0, then explains visits DARAM, uses the visit data directly the instruction; Needs 16 bit addresses are the first 15 addresses, the top digit make up zero, and finished.
③Orders the page address with PORTW to deliver (I/O space address which the register assigns), page address also in SRAM high address wire.
④The use visit data’s instruction, needs again 16 bit addresses are the first 15 addresses, the top digit make up zero.
To memory’s management, needs to compile the ration the procedure. May establish a global variable memory page address. Because the expansion page is only 32K, is bigger than 32K the array is cannot open, therefore use chain table. What needs to pay attention when is releases the space, has not connected a bulk as far as possible the neighboring use’s space, simultaneously needs has used the storehouse copy to pile one after the other spatial the rear part, causes a oneself spatial clustering bulk.
Figure 2, chart 3 respectively be the exterior program extension and data space expansion schematic drawing.
1.2 RS232 correspondence connection software and hardware design
This system uses MAX3110E to connect DSP and PC machine, compared to may obtain general 300baud~230kbaud through the software control frequency division the baudrate. MAX3110E internal UART and the RS232 transceiver can the independent working. The McBSP clock stops the pattern being possible compatible SPI main - from the agreement. The so-called McBSP clock stops the pattern will be refers to its clock when each time the data transmission conclusion stopping, and when the next time data transmission started started immediately or extends a half cycle to start again. Its receiver and the transmitter are the synchronization, namely CLKX and FSX separately are connected with CLKR and FSR; In the transmission process, CLKX and FSX separately use to make SPI shifting clock SCK and enable SS from the side, may be the output (the host’s side), may also input (from side). Its McBSP initialization programming should observe the following several steps:
①In SPCR XRST, RRST set at are 0, is at the reset state.
②McBSP maintains the replacement under the condition, establishes the related register for the value which needs. Because the SPI agreement requests McBSP before the shifting output data, the FSX signal must produce FSX by DXR->XSR, therefore in the XCR register the XDATALY position must establish is 1.
③Establishes SPCR->GRST is 1, the sampling rate generator withdrawal reset state, starts to work.
④Waited for that two clock cycles, guarantee McBSP in the initialization process the interior to be able correctly the synchronization.
Then, disposes MAX3110E the baudrate and the transmission profile, transmits when the data assembles 16 characters according to the MAX3110E data book to carry on the transmission. The receive carries on processing through the DSP Int0 interrupt.
1.3 main line controls and actuation
In this system the main line has two kinds: Data bus and address bus. The data bus carries on the data exchange, the address bus carries on the addressing. Because the DSP data bus is the 3.3V high level logical value, possibly appears cannot actuate exterior 5V the logic level situation; Moreover connects in the dynamic energy is insufficient. Therefore, needs to the main line, specially the data bus to carry on strengthens the driving force the design. And the data bus uses SN74LVTH16245 to carry on the actuation to the actuation; The address bus is unidirectional, does not have the direction control, also has not enabled the control, used the SN74LVTH16244 unidirectional driver to be possible. Regarding data bus’s control, has used DSP_MSTRB reasonably according to logic. DSP_IOSTRB, R/W might complete.
1.4 keyboards and LCD connection hardware designs
The keyboard and LCD are the I/O components, assigns two I/O spaces the address, through produces to the address decoding enables to control LCD and the keyboard. On the keyboard has 12 pressed keys, pulls high with 10kΩ the resistance, simultaneously uses and logical link these 12 lines, the output logical electricity butts DSP to interrupt Int2, uses PORTR in the interrupt service to order the read-in key value. LCD uses in demonstrating the contact surface information. This system uses the LC1611 character lattice module.
1.5 fingerprint image gain
Uses Altera Corporation’s Maxplus II software to carry on the VHDL language programming. According to certain succession, in the fingerprint image multiplication SRAM fast address, this part of debuggings is somewhat troublesome, may place does finally, but the image gain may use under CCS2.0 file->data->load the memory region which puts in the image document assigns. This image document is the CCS data file, may compile a section of C procedure BMP the file conversion CCS document. Another quite convenient method is compiles a script with DSP, uses functions and so on fopen(), fread() the image read-in memory, then uses file->data->save to preserve the CCS document.
2 software designs
2.1 master routine flows
The main flow is must realize a various part of program linking organic whole, and can realizes through the liquid crystal display and the small keyboard response with user’s interaction. Therefore, its duty is can respond the small keyboard, according to the different key value execution different operation, simultaneously demonstrates the different page. System main flow as shown in Figure 4.
2.2 keyboard interrupt routine
in 5402 and interrupts the related register to have three: IFR, IMR, PMST. In DspInitial () in the function, must first establish these registers, then reads in the key value in the interrupt routine. In order to prevent to trigger by mistake, in interrupt time delay 3ms from the very beginning. Its core code is as follows:
ioport unsigned char port0000;
volatile unsigned int* IMR= (volatile unsigned int *) 0×0000;
……
volatile unsigned int* PMST= (volatile unsigned int *) 0×001D;
main() {
DspInitial();
……
}
interrupt void isr_int0() {
delay3ms();
KEY=port0000&0×0FFF;
Switch(KEY)
……
}
2.3 BootLoader programming
This system for the smallest system, needs to be separated from the development system movement, must therefore carry on the BootLoader design. The electricity later automatically will read on the system the procedure and the data from exterior memory Flash in SRAM, but the question was the user program has surpassed 32K, below must therefore use the special BOOT method.
①Internal BOOT. Uses the BOOT procedure which the internal BOOT procedure will establish from Flash to move to internal RAM.
②User BOOT. After internal BOOT completes, starts to carry out own BOOT procedure. Using DSP expansion addressing method, from has established in BOOT programming from Flash read code.
③After user BOOT completes, jumps starts to the user program to move.
2.4 fingerprint recognition core algorithmic routine
This system use’s fingerprint algorithm mainly divides into five parts, its algorithm’s reliability isual C 6.0 had already carried on the confirmation, the concrete algorithm is as follows:
①Background separation. Uses the standard deviation threshold value track law, the image fingerprint part is composed of the black and white same texture, the gradation change is very big, has the big standard deviation; But the background partial gradation distribution is quite smooth, the standard deviation is small, therefore calculates take each spot as a central group of picture element standard deviation, when the standard deviation is bigger than some threshold, may determine that this spot is a prospect, otherwise is a background.
②Computation directional diagram. Uses based on the normal vector method, also involves to field of directions smooth.
③Direction filter. Designs a horizontal template, then revolves the horizontal template to the direction which must strengthen carries on the filter.
④Singular point examination. Differentiates the extraordinary point of difference, like nuclear shape (core), triangle (delta), turbine wheel shape (whorl).
⑤Characteristic point extraction. Uses the keel track law, its basic philosophy carries on the crestline track directly to the image, examines the characteristic point in the track process. The above is uses the fingerprint algorithm the core thought.
Divides into the DSP programming it five duty modules, each module must pay attention to the page register’s value, if the procedure only the movement can waste the massive clocks in SRAM, therefore puts in the subprograms and the data DSP. According to own programming’s experience, the procedure and a data continual processing cannot surpass 64K, therefore may the core procedure resident 5402 in 1K space, leave leeway again the procedure which the 7~8K space transfers needs, in addition 7K uses in storing the data. But considered this method programming the complexity, only uses in the image filter, is simple because of the filter method and is orderly. In order to raise the efficiency, may open two memory blocks (PING-PONG), when uses in the DMA transmission, in addition lets DSP carry on the computation together. Last spot, because 5402 are the fixed point, must therefore carry on the calibration to the overall system.
3 system debug method
After designing and processes the good print circuit wafer, entered the hardware debug stage. First deals with the circuit wafer to make the careful routine inspection, prevents the short circuit and the abruption situation occurrence. After adding the electricity, whether the inspection crystal does vibrate, repositions whether correct reliable, then uses the oscilloscope to inspect 5402 output clock CLKOUT whether to defer to assigns the clock pattern work. Is being these inspection guest, may enter the system hardware debugging stage. When hardware simulation, must first dispose target system’s memory reflection, this is realizes through the establishment simulator command file. May rewrite emuinit.cmd under the simulation debugging software table of contents, causes it each time starts when the simulator autoloading, may also after starting the simulator the manual load command file initialization goal memory reflection. Generally speaking, the simulator memory reflection should be consistent with the coupling memory reflection. To the SRAM debugging’s basic philosophy is, first to the SRAM two unit initialization is two different values, then debugs the master routine takes turn unceasingly these two unit value. The concrete method is reads in another unit from one unit readout, takes the transmission unit by the accumulator. Uses the Debugger software, examines the corresponding SRAM unit, if truly will illuminate the hypothesis to change alternately, then indicated that this part does not have the question. Regarding the keyboard and the LCD debugging, its method is not difficult, here no longer in detail elaborated.
Conclusion
This system has the very strong usability, has manifested the DSP formidable value operational capability fully; But this system has only realized software and hardware’s preliminary development and the development, also has section of distances to the production, but also many work need to do.
