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Abstract: Elaborates in VHDL the Loop sentence dynamic expression to be possible the comprehensive question, proposes three solutions: The direct substitution, the boundary expansion law and the counter law, and contrast these three kind of methods the serviceability. Key word: VHDL Loop dynamic condition synthesis subset direct substitution boundary expansion law counter law Introduction VHDL is one kind of hardware description language, in 1983 by the IEEE formulation for international standard IEEE1076. In recent years the domestic introduction and has published many teaching materials, enables it in domestic to obtain the rapid promotion. Because the VHDL initial goal is to realize hardware’s modelling to propose that therefore its measure ability has overstepped the digital logic integrated circuit’s scope. But the existing EDA tool basically can only support VHDL the subset, specially aims at the different comprehensive tool which the FPGA/CPLD component carries on, its synthesis subset unifies by no means that many beginners are very difficult to grasp. Even if is the part experienced designer, can involve the cyclic sentence regarding the usual higher order language, often cannot handle skillfully in VHDL, even is unable to express this kind of logic, thus has limited the VHDL application level. For example, the VHDL parallel pile of sorting description is a quite typical example. This example is very similar the usual construction of data the description, the promoted prospect is attractive; But can only through the simulation, actually not be able to carry on the synthesis in the present any EDA tool, causes not use value. Does this article involve most Loop sentences from the higher order language to embark, how discusses solves this kind of problem in VHDL. 1 is unable the Loop dynamic condition which synthesizes In VHDL the Loop expression has three kinds to manifest the form: While ……Loop, For ……Loop and independent Loop sentence. It also supports Next, Exit and the marking, therefore, cyclic sentence’s power of expression is bigger than conventional C or the PASCAL language. The procedure 1 is uses for sentence and the While sentence description insertion algorithm partial codes. The procedure 1 cannot be synthesized VHDL cyclic sentence …… for I in 2 to Length loop —Length is a variable Temp:=MyList(I); J:=I; While(j>1)and MyList(j-1)<Temp loop MyList(j):=MyList(j-1); j:=j-1; End loop; MyList(j):=Temp; End loop; …… Regarding the first For sentence, EDA when tool Synplify synthesis will give the non-boundary the scope to prompt wrongly. @E: “H: .vhd “|for loops with unbound ranges should contain w wait statement Even if the part outstanding comprehensive tool, for example ORCAD Express, Mentor Grpahs QuickHDL and so on can synthesize the first For sentence, is also unable to support the second While rule expression. ORCAD Express will give the expression not to be possible the static computation wrong prompt. . .vhd(45):Error,expression does not evaluate to a constant. Because the procedure 1 looks like in the C programmer does not have the question, therefore, the beginner often cannot solve this kind of problem, thus causes the study to fall into the difficult position, is unable to indicate logic fully using VHDL. 2 direct substitution law Regarding the first kind of non-boundary’s scope wrong question, may use the circulation the comprehensive mechanism to transform as the corresponding sentence. For example following code: for I in 0 to 1 loop Out_Bus(i)<=In_Bus(i); End loop; After its corresponding synthesis’s electric circuit see Figure 1. Corresponding, may also use the following sentence to substitute the substitution directly: Out_Bus(0)<=In_Bus(0); Out_Bus(1)<=In_Bus(1); The procedure 1 may use following VHDL code to indicate: K:=2; Temp:=MyList(2); If(MyList(1) <Temp then MyList(2):=MyList(1); J:=1; End if; MyList(J):=Temp; J:=3; Temp:=MyList(3); If(MyList(2) <Temp then MyList(3):=MyList(2); J:=2; End if; If(MyList(1) <Temp then MyList(2):=MyList(1); J:=1; End if; MyList(J):=Temp; …… However, this application method requests the designer to circulate clearly the number of times which the condition certainly will carry out, will otherwise be unable to implement. When the cycle-index is quite big, the code compilation work load will be very huge, therefore may use the second method - - boundary expansion law. 3 boundary expansion law The boundary expansion law is refers to the boundary not fixed time, may decide as the boundary the most greatly possible scope, namely substitutes with the static expression. For example the procedure 1 code may rewrite is: constant MAX:integer=100; –MAX must be bigger than MyLen all possible values …… Out_loop:for I in 2 to MAX loop Exit out_loop when I>MyLen; –MyLen is a variable Temp:=MyList(I); countj:=I; inter_loop:for j in I downto 2 loop countj:=j; exit inter_loop when MyList(j-1)<Temp; –Withdrawal circulation MyList(j):=MyList(j-1); End loop; MyList(countj):=Temp; End loop; Although this method may process the unknown boundary and the undecided expression situation, but consumes the space, when MyLen relative MAX is quite specially small, the price is big. This time, may trade spatial using the time the method to carry on the transformation. Figure 1 For sentence comprehensive demonstration 4 counter law The counter law is the direction stylish clock and the counter, carries on the control with the counter to the boundary condition, may also transform the dynamic expression direct substitution the corresponding static expression. For example, above code’s For condition may use the following code to replace: if (Reset=’1′)then I:=2; Elsif clk=’1′and clk’event then Temp:=MyList(I); J:=2; While(j>1)and MyList(j-1)<Temp loop MyList(j):=MyList(j-1); j:=j-1; End loop; MyList(j):=Temp; I:=(I 1); If(I=MyLen 1)then I:=2; end if; End if; Compares the original code, has introduced 1 clock and 1 replacement. But the synthesis expenses biggest cyclic sentence has been substituted actually for, therefore, the synthesis will have the gate number to drop large scale, but the process time will lengthen correspondingly to the original circulation condition scope. This publication network supplemented that the version (http://www.dpj.com.cn) has published four source codes, respectively be may not synthesize the example, the direct substitution law, the boundary expansion law and the calculator law, the interior has the corresponding annotation. And counter law improvement for double counter method. Conclusion The above three methods have the good and bad points respectively, cannot be generally spoken, may act according to actual situation processing. The direct substitution law uses in the cycle-index few situations generally; The boundary expansion law uses when generally the cycle-index close biggest boundary; The counter method uses in the chip internal clock relative signal clock quick many situations generally. |
