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 Abstract: Introduced based on DSP the chip TMS320F206 electrical network sampling processing board’s software and hardware design method, has made the key discussion to the hardware various modular circuit’s principle of work, simultaneously has given this electrical network data processing board master routine and the interrupt handling routine flow chart.

    Key word: TMS320F206; MAX125; 16C552

1 introduction

Along with the electrical power system new load and misalignment load’s massive increase, electrical power system’s voltage and the current waveform will have the serious distortion, will thus very in a big way bring very in a big way “the electrical network pollution” for the electrical power system. Specially the user interior short circuit as well as on-off operation, the transformer or the condenser bank will throw will cut when the short-time interrupt to cause the transition condition, the instantaneous overvoltage as well as the voltage are hollow, electrical energy quality perturbation questions and so on bulge or short-time power failure. Simultaneously in the electrical network system’s overtone ingredient is also getting more and more complex, the serious electric power “the pollution” to certain professions (for example hospital precision instrument, micro computer system as well as intelligent electron, in commercial run control’s microprocessor and so on) posed the huge threat, even creates “the waterfall” the type chain-like reflection, thus causes the event which the electrical network collapses. Therefore, in the electrical power system electrical network data’s precise gathering, the breakdown judgment, the data processing have become the electrical network correct movement the focal point.

    The existing electrical network quality analysis board the component and analysis method’s limit, to system’s transition condition, the short-time perturbation information with difficulty is mostly fast, catches accurately. Along with high speed figure signal processing 煟 mold cherry school 牸 border acyl⒄Gu eight washed with watercolors the garden fei to kill the mirror to admire the files to stop the DSP technology to obtain the widespread application in electrical power system’s each research area. Table 1 is the DSP way and the traditional chip processing mode ability contrast, may see DSP to serve as processor’s superiority.

Table 1 DSP and traditional chip handling ability reference table

2 based on TMS320F206 hardware design

Is uses DSP based on the DSP processing board’s main body design concept the chip TMS320F206 constitution digital processing system, and realizes the real-time sampling, the data processing, the analysis and the short-time storage take the lower position machine as the main body, then carries on the data communication with the superior machine, as well as carries on the demonstration and the database store management using the long-distance computer and so on. The concrete operations are as follows:

(1) surveys and calculates the three-phase current, the voltage effective value, the active power, the reactive power as well as the power factor with the processing board; Carries on the frequency measurement sampling to the 40Hz~2MHz frequency input signal;

(2) carries on processing to the data, the analysis looks up wrong, gives the warning category, and gives the switch quantity output signal in order to carry on switches on the operation;

Figure 2

    (3) to the voltage, the electric current l~63 subharmonic carries on the analysis, gives the scope, the phase as well as the three-phase voltage, the electric current total distortion factor;

(4) expands 2 RS-232 and a RS-485 connection through 16C552 chip UART in order to carries on the data exchange with the superior machine, simultaneously expands one parallel is connected by and the printer;

(5) carries on refurbishing, the replacement and the real-time examination system with the watch-dog;

This processing board’s master control chip selects fixed-point DSP chip TMS320F206. System’s hardware function diagram as shown in Figure 1.

This electrical network sampled data processing board’s function is completes under the digital signal processing chip TMS320F206 control. The data sampling module uses 3 piece of high speed 14 A/D chip MAX125 when work external connection and 16C552 public 16MHz clock, because its parallel interface data accessing and the main line release the time response and the DSP characteristic is compatible, therefore, its transformation result may by the DSP waiting status, but reads directly. 3 piece of MAX125 carries on the synchronized sampling in this with 12 groups 煵 to wield Gui to bear ǖ the jail against disturbance to receive. Simulation quantities and so on voltage, electric current transform - the 5V~ 5V voltage through the transformer, and after the filter turns on MAX125, the transformation starts the signal to provide by DSP pin TOUT to 3 piece of MAX125 CONVST pins, and in the rise along the start sampling, the internal succession generator may control the channel which assigns to cause it to carry on the transformation according to the order, and will save finally in internal 14Bit×4 RAM, after the transformation had ended, each piece of MAX125 INT pin changes low 煟 said that gives DSP through the CPLD or gate output. When reads the result, the execution reads the operation continuously, what first time reads is the first channel’s data, what second time reads is the second channel’s data, ex analogia.

16C552 is TI 煟 abundant ta yu bites carries on a shoulder pole vast Bolivia 牎ⅲNiu Wuli the remote 煟 cherry abundant guarantees bites carries on a shoulder pole Bolivia, VLSI 煟 Zheng Tabao to bite vast carries on a shoulder pole vast the asynchronous communication chip which the Bolivian 牭 skirt department produces. 煟 guarantees in the sampling processing board bites carries on a shoulder pole vast bucket chi RS232, the RS485 serial port and the printer and the mouth expansion chip, and comes and the MAX1486 actuation chip and the superior machine through the MAX232 actuation chip carries on the communication. Figure 2 is the circuit diagram which UART expands.

Figure 4

    Because TMS320F206 only has a synchronized communication mouth, thus designs uses DSP the UART expansion. Simultaneously because the input output interface’s resources are limited, therefore has used the CPLD expansion. In Figure 2 DSP and the power source, the electro-optical coupler and so on has made the simplification, has the interest reader to be possible to inquire the correlation data. In this system the 16C552 serial port and the mouth works when the interrupt working, 16C552 CLK the end external connection 15.9744MHz crystal oscillator, may through the establishment divisor register high, low position DLM, DLL determine the communication the baudrate.

In hardware circuit design, l6C552 internal register choice line A0~A2 as well as read-write signal by the DSP positive governing. The string, parallel channel’s piece route selection CSA, CSB and CSP by the CPLD positive governing, may according to need to choose the serial communication way parallel mailing address. For the interference protection, the system has joined the electro-optical disconnector, because the RS232 level and the CMOS level are different, therefore RS232 driver and time CMOS level connection must undergo the level switch, MAX232 completes this function. Moreover, realizes with MAXl486 with the RS485 communication, this actuation chip’s OE, H/F may decide that the electric circuit is the work in the half-duplex or the full-duplex condition, and may control the choice by CPLD. l6C552 and the mouth may on direct connection PC machine and the mouth do not need the level switch. When communication, through interrupts INT1~INT3 to be possible to have the application to the CPLD logic block, and responds by DSP.

    For ease of debugged and realizes functions and so on program load, establishment software break point, the system expands 32k fast SRAM to come the procedure, the parameter to put in which, after debugging successfully, might wait the solidification procedure to burn into through the simulator in TMS320F206 first 16k character Flash, second used in solidifying the laying aside key parameter. In order to debug convenient and the effective use resources, the procedure, the data select patches or strips of land as worth saving for seed should use the connection mode which shown in Figure 3, when the debugging before the procedure selects, 16k (8000H~BFFFH) SRAM, latter 16k (C000H~FFFFFH) uses in depositing the data parameter.

This system can survey 40Hz~2MH the signaling frequency. When surveys the power frequency, electrical network signal after transformer voltage dropping, again gives CPLD after the filter and the comparator to carry on the counting survey. 8MHz (CLK) the crystal oscillator pulse input may use the independent active crystal oscillator, may also use CPLD to obtain to the existing 16MHz crystal oscillator frequency division.

Selects completes watch-dog replacement chip MAX1232 which the system power source monitors, may establish as automatic refurbishing and the hand reset union way. when the voltage detector monitors the allowance which Vcc is lower than chooses, the system will output and will maintain the replacement level; Enables DSP in certain time internal trigger ST end refurbishing watch-dog. If ST has not triggered in the 250ms gap, the MAX1232 automatic discrete sampling repositions the system.

3 based on TMS320F206 software flow

This data acquisition processing board starts A/D through the TMS320F206 interior timer interrupt to transform, the interrupt cycle is established as each cycle sampling 64 spots, namely approximately 312.5ns triggers an interrupt. After the MAX125 12 group A/D transformation completes, the electric circuit will trigger signal of stop INT0 to give DSP. The real-time data through read the pulse from DSP to save continuously the data to, exterior expand RAM or pass to through the communication expansion chip the superior machine. After the data sampling achieves 64 spots, starts to carry out the FFT unit. Usually saves the FFT algorithm block to DSP in interior memory cell B0, this unit is 64 spots with the site base 2 time extraction FFT module. May realize through the DSP algorithm to each electrical energy qualitative index and other electrical parameter computation and the analysis, simultaneously carries on the data processing (including wave analysis and unbalancedness analysis), is also when the sampling point sampling well off information and so on detection signal’s peak value, effective value, have judged electrical energy quality questions and so on pressure, undervoltage, vibration. Finally real-time waveform either analytical spectra readout to the PC superior machine or in other networks. System’s each sampling period’s time distribution see Figure 4 to show. Its software master routine and the interrupt handling routine flow chart see Figure 5, shown in Figure 6 separately.

4 concluding remark

Our country is late to the electrical network quality research start, at present uses the electrical network quality detection equipment and the developed country also have certain distance, therefore, the electrical network contamination concern still waited for further solves, the traditional sampling apparatus waits for further optimizes enhances, this article designs the electric power sampling processing board uses the DSP chip constitution digital processing system, realizes the real-time sampling, the data processing, the analysis and the short-time storage take the lower position machine as the main body, simultaneously carries on the data communication with the superior machine and uses the long-distance computer demonstration and the store management database. The experiment proved: May raise system’s operating speed and the precision using this equipment 煻, and the performance-to-price ratio is very high.