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Introduction
—TMS320VC5402 (hereafter refers to as C5402) is fixed point digital signal processor (DSP) which the Texas Instruments company in 1999 promoted. Compare with TMS320C54x series’s other chips, C5402 the high performance which, the low power loss and the low price is in sole possession of by it have received people’s widespread favor. The C5402 enhancement peripheral device has the software waiting status generator, the phase-locked loop clock generator, 6 channel direct memories to visit the (DMA) controller, enlargement mode 8 bit parallel host interface (HPI) and so on. Two programmable multichannel cushion serial port (McBSP) can the full-duplex, carry on the data exchange fast with other synchronized serial port, the hardware connection is simple, the serial port working pattern and the transmission data’s form may realize through the programming.
—Because the C5402 interior has not integrated A/D, therefore in data acquisition time needs to use a/D transformation chip, a/D chip and the C5402 connection designs into an important question. A/D transformation chip has serial A/D and parallel A/D generally. To use the multichannel cushion serial port resources which fully C5402 provides, the simplified system design, this article system used TI Corporation’s high speed serial A/D simultaneously to complete two group data acquisitions, raised the serial port working efficiency greatly.
Serial A/D chip TLV1572
—TLV1572 is the high speed ten serial bit A/D transformation chip, may directly is connected through 3 either 4 serial port lines with DSP or other digital microprocessor serial port, does not need the sur- logic, but conversion rate SCLK supplies clock’s limit. TLV1572 and the DSP multichannel cushion serial port connected is through CS, SCLK, DO and the FS four lines completes, this time DSP CLKR produces the shift pulse, FSR produces the frame synchronizing signal, and provides separately to TLV1572. When T-LV1572 connects with other serial port microprocessor FS must provide the high level, through CS, SCLK, the DO three lines completes the data transmission. When CS is high, A/D chip various base pins are at three condition conditions. When CS by Gao Biandi, TLV1572 examines the FS pin the condition to determine the working pattern, if FS is low, is the DSP pattern, if FS is Gao Zewei other microprocessor pattern.
Figure one TL1572 under DSP pattern transformation succession chart
Figure two TL1572 under microprocessor pattern transformation succession chart —When TLV1572 work when the DSP pattern, must guarantee when CS changes is low, FS is the low level, and must lock saves certain time. CS is when is low, DO jumps out three condition conditions, when is high the chip is separated from the dormant state until FS. TLV1572 along examines FS in each clock SCLK drop the condition, once examines FS is high, TLV1572 starts the sampling. In the FS drop along, a/D chip through shifts the clock to transfer to the data on DO. After 6 leader 0 transmissions, DSP may along obtain the data which in clock’s drop A/D transforms, as shown in Figure 1. After most low position emigration, a/D chip enters the dormant state automatically, until the FS next effectiveness. If FS after 16 transmissions complete is effective immediately, then A/D starts the recent data conversion, this time A/D is transforms continuously. If FS changes high in the TLV1572 transformation data’s process, then a/D chip is repositioned, starts the recent data conversion cycle. Therefore may through establish FS, changes the data transmission the figure.
—When TLV1572 work when the non-DSP pattern, the FS pin must meet the high level. In each time transforms in the process must provide 16 clock signals, if the microprocessor is unable a time to receive 16 bit data, may divide into 8 two receives, two times receives the time-gap cannot be bigger than 100μs, this time CS must be at the effective condition. The start which transforms under the DSP pattern is by the FS signal effective decided that but under the microprocessor pattern, after the data conversion CS effective first clock signal rise along starts, as shown in Figure 2. Under microprocessor pattern, may also through establish CS to change the transmission the figure.
C5402 multichannel cushion serial port
—C5402 provides two high speed, the full-duplex, multichannel cushion serial port McBSP0, McBSP1, with the data line D(R/X), frame synchronization line FS(R/X) and the shifting clock line CLK(R/X) realizes the transmission data and the receive data. McBSP passes 6 pins (DX, DR, CLKX, CLKR, FSX and FSR) and the peripheral device connection.
(1) CLKX (transmission clock input or output)
—The chip internal transmission thought that register (XSR) transmits through this clock signal the data to the DX pin. This serial port may position dispose the use internal clock through PCR register’s CLKXM or use the external clock.
(2) FSX (transmission frame synchronization input or output)
—FSX is the symbol which the transmission starts, the serial port may position dispose the input or the output through PCR register’s FXM.
(3) DX (serial data transmission)
—The serial port data transmission is carries on through this mouth.
(4) CLKR (receives clock)
—CLKR uses for to receive the external clock signal, this clock signal moves in the DR data receive shift register (RSR). May position dispose the use internal clock through PCR register’s CLKRM or use the external clock.
(5) FSR (receive frame synchronization input)
—The FSR receive frame synchronization signal impulse, symbolizes the data receive start. May position dispose the input through PCR register’s FRM, may also dispose the output.
(6) DR (serial data receive)
—The serial port data receive is carries on through this mouth. In the receiving process, the data first moves in RSR through under the shifting clock CLKR function (receive shift register), then, in the RSR data again copy to DDR (data receive register), when the copy completes, has the RINT interrupt to inform CPU to respond or the REVTA interrupt informs DMA to respond, simultaneously establishes RRDY to interrupt the flag bit, may also use the inquiry way to complete, from data register readout. CLKX, CLKR, FSX, FSR namely may by the internal sampling rate generator production, may also actuate by the external instrumentation. McBSP along along carries on the data detection separately in the corresponding clock’s rise with the drop. Each McBSP are most may support 128 channel’s transmissions and the receive, the serial word length may elect, including 8, 12, 16, 20, 24 and 32, but also supports Mu rate and a rate data compression expansion.
System hardware design
—After having analyzed the C5402 multichannel cushion serial port and serial A/D the switch TLV1572 operating feature, may use the TLV1572 work in the DSP pattern, causes it to carry on the connection with C5402, completes the data transmission which under the synchronized clock signal’s function A/D transforms. Figure 3 is the entire data acquisition system’s hardware schematic diagram, this system acts according to C5402 the multichannel cushion serial port characteristic, uses two cushion serial ports to carry on the data transmission fully with two piece of serial A/D TLV1572.
—In order to achieve with C5402 is very good matches, a/D power source and the reference voltage have met 3.3V. A/D FS meets DSP FSX and FSR, causes the data feeds the frame synchronizing signal to produce by DSP. SCLK meets DSP CLKX and CLKR, such data’s input and the output clock come from DSP. C5402 when carries on the data transmission with two piece of A/D, the establishment serial port interrupts the work in 00 patterns, namely the serial port data arrives at triggering to interrupt, which piece of A/D transmission data such can CPU act according to produce the corresponding serial port to interrupt RINT0 or RINT1. When two serial port’s data also arrive, when namely simultaneously applies for the interrupt, C5402 CPU will respond the RINT0 interrupt according to the interrupt priority, will then respond again interrupts RINT1. In order to guarantee that the data communication the reliability, avoids the data conflict, in responds the RINT1 interrupt in the process, serial port 0 non-interrupt requests.
—In the C5402 chip the disposition has 4K×16bit the internal protected type ROM(F000-FFFF). Resources has contained the Bootloader procedure in 4K in the ROM, exterior it allows the procedure to place in the slow memory or the microprocessor, and adjusts in the high speed DRAM memory to move, reduced the C5402 interior mask need greatly, reduced the circuit design cost. System independent working’s internal logic completes by CPLD, as shown in Figure 4.
 —On when C5402 electricity replacement loading, because Bootloader procedure in initialization time establishes XF is the high level, after the system enters the parallel guidance loading pattern, C5402 from the data addressing is the 0FFFFh unit (A15=1, selects procedure memory block first address which Flash) the read is going to write down, with parallel reprint data stream. This time, C5402 may unit data read AT29LV1024 Flash in the address 08000h~0FFFFh C5402 to correspond outside 0000h~7FFFh addressing area internal DARAM and the piece in SRAM IS61LV6164.
—After the Bootloader procedure had ended, in this system, the user program’s first sentence is RSBX XF, namely sets at the XF pin is the low level, Flash does not select throughout. Thus, the SRAM high 32K region (08000h~0FFFFh) is released, may take when the DSP systems operation data area or procedure area use.
System software design
—System’s software design mainly includes the multichannel cushion serial port the initialization, the serial port interrupt service and the parallel loading operation design and so on.
* the programming should pay attention question
(1)McBSP work in data receive interrupt mode, therefore the overall situation interrupt and the serial port interrupt’s corresponding position should establish reasonably. At the same time, when establishment interrupt to meter, causes the interrupt corresponds to meter’s position and in processor pattern condition register PMST interrupt vector indicator IPTR, causes IPTR 9 bit address to aim at the procedure page which 128 characters the interrupt vectors are, simultaneously, interrupts to the meter must strictly according to the C5402 stipulation form compilation, otherwise cannot have the interrupt result which correctly needs.
(2) must realize the DSP data acquisition system’s off-line independent movement, needs to give each DSP to provide the independent program memory, when overall system electricity or replacement, will save Yu Pianwai the procedure code from the guidance loading operation to load to internal DARAM or in system’s expanded memory unit, then the operating procedure completes to McBSP carries on the establishment and other procedures.
(3) to realize between two group A/D and the C5402 succession matches, avoids the data conflict, needs to pay attention to the C5402 sampling rate to have in register SRGR1 the CLKGDV position establishment, causes C5402 to work the clock cycle to be bigger than two serial port interrupts the response time.
If TLV1572 calculates by the 400KSPS slewing rate, each piece of A/D should be each 2.5μs transmits one time to DSP the data, the application interrupt, the CPU response interrupt receives the data. DSP work when 100MHz, the clock cycle is 10ns, therefore in each cushion serial port interrupt service may carry out one to be short in 125 clock cycle procedure, but does not affect the serial port the receive, if the serial port interrupt routine’s time is insufficient, but may also cut a/D slewing rate suitably, is the serial port interrupt provides the longer interrupt servicing time.
* serial port receive part initialization routine
—Below according to the multichannel cushion serial port’s characteristic and two group serial A/D work’s request, mainly introduces the serial port receive the software design and the serial port partial key establishment.
; ===== initialization serial port 0=====
stm #0, SPSA0
stm #0000h, SPSD0; #0000H reads in SPCR10
stm #1, SPSA0
stm #0000h, SPSD0; #0000H reads in SPCR20
stm #2, SPSA0
stm #0040h, SPSD0; #0040H reads in RCRC10, each character 16
stm #3, SPSA0
stm #0040h, SPSD0; #0040H reads in RCR20, each section, each section of character
stm #6, SPSA0
stm #000fh, SPSD0; #0009H reads in SRGR10, clock cycle CLKG=6.4MHz
stm #7, SPSA0
stm #300fh, SPSD0; #3010H reads in SRGR20, the frame period is 16 CLKG
stm #0eh, SPSA0
stm #0a04h, SPSD0; #0A04H reads in PCR0, FSX, the CLKX output, the FSR, CLKR input
; ===== initialization serial port 1=====
— The serial port 1 initialization routine see also the serial port 0
; the ===== start receives =======
stm #0, SPSA0
stm #0001h, SPSD0; Start serial port 0 receives
stm #1, SPSA0
stm #00c0h, SPSD0; The interior produces the clock to produce FSG
stm #0, SPSA1
stm #0001h, SPSD1; Start serial port 1 receive
stm #1, SPSA1
stm #00c0h, SPSD1; The interior produces the clock to produce FSG
; == serial port 0 receive interrupt subroutine ===
.sect “brint0″
host_brint0:
rsbx intm; Closes the interrupt
ldm drr0, A
stl A,*ar4 ; Receive
……
Other disposal procedure
rete
Concluding remark
—This article introduced two piece of serial A/D and the C5402 composition’s data acquisition system, this system hardware connection is simple, a/D sampling rate may establish nimbly through the serial port clock, versatile. This data acquisition system already succeeded applies the laboratory in the signal processing system, demonstrates the design nimbly, high speed, reliable and so on merits.
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