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    Abstract: In view of the fact that the MCS-51 system only provides “the second-level interrupt nesting”, proposed that expands 51 system outage priorities the pure software method. It uses interrupt permission register IE which and interrupt priority register IP in 51 systems constructs, realizes through the shield character mechanism; By the C51 form, gives this expansion method the function storehouse to realize, in a friendly way entrusts with, the succinct user interface for this method’s use.

    Key word: The MCS-51 monolithic integrated circuit interrupt priority expands C51 softly

Introduction

It is well known, the MCS-51 system only provides “the second-level interrupt nesting”, but the majority embedded systems hoped that has is more than two levels of first ranks. Because of generally speaking, the system has the power failure interrupt, and should set for the highest priority, like this possesses other interrupts only to be able to use in common a lowest priority, so, often cannot meet the actual logical need. In order to enable the system to have is more than two level of interrupt first ranks, may realize the interrupt priority hard expansion using the 8259A and so on interrupt control chip, but actually increased system’s construction cost and the complexity. Because of the complex enhancement, system’s reliability will come under the influence. This article proposed that one kind expands the MCS-51 system outage priority the pure software method, cannot increase any hardware, and needs the extra resources consumption is also very small. The practical application indicated that this method is feasible and effective.

1 MCS-51 interruption system synopsis

The MCS-51 series monolithic integrated circuit permission has five interrupt sources, provides two interrupt priorities, may realize the second-level interrupt nesting. These two levels of priorities follow following rule: Only the high priority interrupt source may the interrupt nesting low priority interrupt source. In order to realize this rule, the interruption system interior contains two not addressable priority condition trigger. When specific priority’s some interrupt source is responded, the corresponding trigger namely by the setting, after having carried out the RETI instruction, this trigger only then repositions. , Same level and the preliminary interrupt will be prevented. Whether does the interrupt source interrupt request obtain the response, is interrupted permission register IE the control. Each interrupt source’s priority may through to interrupt the priority register IP programming to establish: Either lowest, either highest. When identical priority’s various interrupt sources simultaneously request the interrupt, inquires the logical determination response order by the interior. The inquiry order is in turn: The external interrupt 0 (X0), the timer interrupts 0 (T0), the external interrupt 1 (X1), the timer to interrupt 1 (T1), the serial port interrupt (S). If the current instruction is RETI perhaps to IE, the IP operation instruction, will seal CPU to the interrupt response, and after must carry out an instruction, again only will then respond the interrupt.

2 interrupt priority soft expansion method

First, gives the soft expansion the first method, and analyzes its characteristic, points out its existence the flaw. Then, based on to a method deficiency, gives the method two, methods which consummates unceasingly three. And the method two are to a method consummation, the method three are to the method two consummations, and has solved method one, two flaw finally, has realized the true interrupt priority soft expansion.

2.1 methods one

This law only uses and system’s interrupt permission register IE, through the interrupt mask character mechanism, enables the different interrupt source to have the different logical interrupt priority (in as follows “priority” like not to explain that namely refers to “logical interrupt priority”).

Does not lose the generality, might as well makes 8051 system’s five interrupt sources - - outside to interrupt 0 (X0), the timer to interrupt 0 (T0), outside to interrupt 1(X1), timer to interrupt 1 (T1) and the serial port interrupt (S), has priority which like Table 1 arranges in order. (in the practical application, regards the special details, entrusts with the different interrupt source by the suitable priority. )

And, “0″ represent the highest priority, “4″ represent the lowest priority.

First, for established priority various interrupt sources to bestow on by second-level “the physical interrupt priority”: (X1) (PX1) sets at the priority highest interrupt source in the interrupt priority register IP corresponding position 1, but make the IP in other related position (PT1, PT0, PS, PX0) is 0.

Next, for has established the priority various interrupt sources assignment suitably “the interrupt mask character”. Its basic philosophy is the shield same level and the preliminary interrupt. The concrete allocation process is as follows: The priority is k (0≤k≤N-1, N for interrupt source quantity) the interrupt source “the interrupt mask character” is: Priority for x(x∈[k, N-1], namely same level and preliminary) interrupt source in IE corresponding position 0, priority for y(y∈[0, k-1], namely high-level) interrupt source in IE relevant position 1, but results in byte byte. Certainly, the IE EA position (the CPU interrupt permits flag bit) is 1 throughout.

Interrupt priority assignment situation which arranges in order regarding Table 1, various interrupt sources “the interrupt mask character” disposition like table 2 arrange in order.

Table 1 interrupt source priority distribution list

Finally, for various interrupt sources’ ISR (Interrupt Routine, interrupt servicing routine) performs the outer covering which as follows shows (the Assembly form). Might as well take the timer 0 (T0) as the example:

CSEG AT 8×1 3

; The definition absolute section, the establishment breaks the vector

JMP T0_ISR_SHELL

? PR? TO_ISR_SHELL? XX SEGMENT CODE; The statement locates the section again

T0_ISR_SHELL:

PUSH IE; Preserves IE

MOV IE,#TO_INT_MASK

; Establishment current interrupt mask character

CALL ResetIntSys: Replacement interruption system

CALL T0_ISR: Transfer interrupt servicing routine main body

POP IE; Restores IE

RET

Here, T0_ISR is the timer 0 (T0) ISR main body part. Its should by the general function form, with the assembly or the C compilation. ResetIntSys is only contains an interrupt bridging order (IRET) the function, namely ResetIntSys:RETI. It uses in repositioning the interruption system, causes in the corresponding ISR implementation, the system still might respond the interrupt request which other end source proposed, with the aim of realizing the interrupt nesting. This achieved has prevented same level and the preliminary priority interrupt goal.

The high priority’s interrupt source may propose the interrupt request, but will be responded immediately not necessarily. Because under the current strategy, still could not realize “the interrupt nesting” (i.e. high priority interrupt servicing routine to be possible truely to interrupt low priority interrupt servicing routine, but nesting execution), but only has the highest priority interrupt (X1) only then to be possible to realize this kind truely “the interrupt nesting”. Because in 8051 systems, interrupts the nesting only to be whether decided by its correspondingly “the physical interrupt priority” (various interrupt sources physical interrupt priority by the interrupt priority register IP in corresponding position decision, and only has second-level). Below divides a three kind of situation explanation method characteristic and the insufficiency:

①When the external interrupt 1 (X1, it has highest logical interrupt priority and highest physical interrupt priority) proposes the interrupt request, the system will immediately respond, no matter but system this time busy otherwise. If this time system will be carrying out other interrupt ISR, X1 ISR by the nesting form execution, because other interrupt the lake the physical interrupt priority to lowly (51 systems only to have two level of physical priorities: Highest or lowest).

②When the timer 0 (T0, its priority is 2) the interrupt request when responds, from the serial port (S, its priority is 3) and the external interrupt 0 (X0, its priority is 4) the interrupt request will be forbidden; But only permits the external interrupt 1 (X1, its priority is 0) and the timer 1 (T1, its priority is 1) proposes the interrupt request. If is X1 proposes the interrupt request, then X1 ISR immediately nesting execution; If is T1 proposed, although its priority is higher than current interrupts T0, but because its physical interrupt priority and T0 same (with for lowest), will therefore not look like X1 such immediately to respond by the system, and nesting execution, but can only wait for, finished until the T0 interrupt servicing routine execution.

③If in the serial port (S, its priority is 3) interrupts is being responded in the process, the timer 1 (T1, its priority is 1) with the timer 0 (T0, its priority is 2) proposes the interrupt request separately. Because they have are higher than S the priority, therefore the system allows them to propose the interrupt request; But because its physical priority and S are the same, therefore finished until the S interrupt servicing routine execution, the system will only then accept T1 and the T0 interrupt request. In logic, because T1 has is higher than T0 the priority, therefore T1 should be the system response first. But when the physical priority is the same, interrupt request’s response order is decided by the interior polling sequence, but T0 is before T1, therefore in fact T0 the first system response, namely presented “the priority reverse” question.

Obviously, method one, although may achieve “the expansion interrupt priority” partially goal, but it has two problems:

* certain high priority interrupt cannot the interrupt nesting low priority interrupt;

* will present “in the priority to reverse”.

The method two and the method three are aims at method these two insufficiencies to propose that and realizes finally to 51 system’s interrupt priority true expansion.

2.2 methods two

This method is in a method foundation, is the solution “the priority reverse” question, but implements simple strategy.

In the one right “the priority reverse” the question analysis may know according to the method, has this problem the reason is: Various interrupt sources’ logical priority is inconsistent with its interior polling sequence. So long as in system design time, proper attention to both interrupt source dependent event’s urgent degree and interrupt source internal inquiry logic: The most urgent event (for example power failure) will bestow on by the highest priority 0, and causes it the interrupt source which inquires (external interrupt 0<X0>) to be connected first with the system in; Causes an urgent event first is 1, and causes it second the interrupt source which inquires (timer 0<T0) to be connected with the system. Ex analogia, for tightly pursues the degree lowest event to bestow on take lowest priority N-1 (N as interrupt source integer), and causes it the interrupt source which inquires (serial port to interrupt with the system in <S>) to be connected finally, namely in 51 system’s various interrupt sources should have the priority which Table 3 arrange in order.

Table 3 interrupt source priority assignments

So, then solves “the priority reverse” question.

2.3 methods three

This law is in method one, two foundations, in view of “certain high priority interrupt cannot the interrupt nesting low superior grade interrupt” the question, introduces the corresponding strategy, realizes to 51 system outage priorities “true” the expansion.

3 priority soft expansion’s function storehouse realizes

To expand 51 system’s priorities truly, various interrupt sources’ priority, the first cascade screen character, the interrupt mask character should be definite, like Table 3, 4 arrange in order. When the C51 compilation breaks the service routine, should give the corresponding interrupt source serial number (interrupt number). The specific interrupt source has the specific interrupt number, but this interrupt number with interrupts the proper priority to be consistent respectively exactly.

This article uses C51, realizes the strategy which by the function storehouse’s form method three state, it contains two documents: ExtIntPri.H, ExtIntPri.C. Must point out that to cause the priority the establishment and restores has the atomicity by against to have the confusion, deals with SetPriority() and ResetPriority() makes critical processing, causes it not quilt “the re-entry” the visit. Moreover, deals with the system stack to make the adjustment. As shown in Figure 1, “1″ represents the adjustment which SetPriority() does, it IP, IE preservation in system stack; “2″ represent the adjustment which ResetPriority() does, it restores IE, IP from the system stack; “HAddr”, “LAddr” respectively represents the current function return address the upper byte and the low byte (in stack’s address is way saves by small end character order or sequence of the solar terms <Little the Endian>, this is in C51 only exception, but possesses other multi-byte data all by big end character order or sequence of the solar terms <Big Endian> way memory). If not does this, but is defines two global variables to preserve IE, IP, because SetPriority () and ResetPriority() must visit these two global variable, but these two functions should are transferred separately in the ISR switch and the ending place, thus causes ISR to become the critical zone, but cannot by other ISR interrupt, this cause the priority the existence to dwindle.

//ExtIntPri.H

extern void SetPriority (unsigned char);

extern void SetPriority (unsigned char);

extern void ResetPriority(void);

//ExtIntPri.C

#pragma src

#include “ExtIntPri.H”

#include<reg51.h>

// static state (partial) function statement

static void ResetIntSys(void); // only contains an instruction: RETI

// extends two great serve as “the critical zone” enters the area and the withdrawal area

#define ENTER_CRITICAL()EA=0//closes the interrupt, by against critical re-entry

#define EXIT_CRITICAL() EA=1

// interrupt mask character and the first cascade screen character’s great definition, like Table 3 arrange in order.

#define S_INT_MASK 0×8F//; 1-01111B

//…

#define S_PRI_MASK 0×0F//; —01111B

//…

// the regulating system stack preserves IP, IE first, its process as shown in Figure 1, then to assign the interrupt

// (prio is also interrupts number) to establish the priority

void SetPriority (unsigned char prio) {

ENTER_CRITICAL (); // closes the interrupt

#pragma asm

POP the ACC // springs the return address upper byte HAddr

POP the B // springs the return address low byte Laddr

PUSH IP

PUSH IE //EA = =0

PUSH the B //LAddr enters the stack

PUSH the ACC //HAddr enters the system

#pragma endasm

switch(prio) {

case 0:IP=X0_PRI_MASK; IE=X0_INT_MASK;

break;

//…

case4:IP=S_PRI_MASK; IE=S_INT_MASK; break;

}

ENTER_CRITICAL(); // here interrupts is opened, therefore closes the interrupt again

ResetIntSys();

EXIT_CRITICAL(); // opens the interrupt

}

// restores IE, IP from the system stack, its process as shown in Figure 1. This function should in withdraw from time ISP transfers

void ResetPriority(void) {

ENTER_CRITICAL();

#pragma asm

POP the ACC // springs the return address upper byte HAddr

POP the B // springs the return address low byte LAddr

POP IE //EA = =0

POP IP

PUSH the B //LAddr enters the stack

PUSH the ACC //Haddr enters the stack

#pragma endasm

EXIT_CRITICAL(); // opens the interrupt

}

// only contains an instruction: RETI, with repositions the interruption system, so that the system can may respond other interrupts in the ISR implementation

void ResetIntSys(void) {

char code reti=0×32; //32H is the RETI machine code

(((void) (code*)(void)) (&reti)) (); // transforms the reti address compulsion as the function indicator

}

When use, only need join a ExtIntPri.H document with #include the corresponding source document (certainly, should ExtIntPri.C object file <*.Obj>, storehouse document <*.lib> or assembly source document <*.src> joins current project). Might as well take the timer 0 (T0) as the example, its interrupt number is 1, therefore the priority should also be 1, as follows shows:

////Test.C

#include “ExtIntPri.H”

//…

void T0_ISR(void)interrupt 1 using 2 {

SetPriority(1);

//…

ResetPriority();

}

So, T0 namely had the time highest priority - - 1.

Conclusion

Use this article states “the soft expansion” the method, may expand the MCS-51 system’s interrupt priority to 5 levels. If uses 51 system’s interrupt source integers is N (N≤8), only need make the revision to the above method then to expand slightly its priority to the N level. This method cannot increase any hardware, and needs the extra resources consumption is very small, the use is also simple, will not increase the programming burden to the user. The practical application indicated that this method is feasible and effective.