Abstract: Introduced that one kind take MCS51 as a nucleus, in addition FSK, DTMF, foreign electric circuits and so on digital modulation/demodulation compose control system. In the similar control system, how to satisfy the system request, and how compatible and reduces the system area with the MCS51 microprocessor is in the design two big key questions. Through analyzes MCS51 the instruction and the succession relations, designs has the proprietary intellectual property rights with the MCS51 compatible microprocessor, completes it and the foreign electric circuit integration and from test circuit’s insertion. This system has carried on the layout wiring and the latter simulation separately in FPGA and in the gate array, and passed the FPGA prototype prototyping testing.
Key word: SFR special function register FSK frequency-shift keying DTMF double sound multi-frequencies
Introduction
Along with the telecommunication market’s day-by-day opening, the competition, an operator surface clam more tremendous pressure, must raise the capital pay-off efficiency, enhances fixed-line telephone’s ARPU value. China moved the short information service which promoted to obtain the very good economic effect and the social efficiency, the short note by its unique quickly and convenient, was affecting people daily life many aspects. “the fixed-line telephone informationization” and related standard’s releasing, fixed-line telephone’s manufacturer also promotes the similar service, thus realizes the traditional telephone’s increment.
But the solid net short note has two aspects “the bottleneck”; Has the flaw in the terminal and the content. In the terminal aspect is the price question, should consider how to fall the price to the user acceptable scope.
This system is aims at such market demand to design. It needs 1 to satisfy the system request the microprocessor, 1 big fonts to support. At the same time, this chip must control under certain area, reduces the cost.
This article will introduce and in the MCS51 compatible micro controller’s design and the DTMF decoding data processing emphatically.
1 and MCS51 compatible micro controller design
Intel the MCS51 series is one kind of 8 microprocessors. The exterior procedure and data-carrier storage’s addressing range may achieve 64K.MCS51 to have 5 interrupt sources, 2 for the exterior interrupt source, each interrupt source’s priority are programmable. In order to meet the solid net short note system function need. Mainly carries on following three aspects to MCS51 the expansion. SFR expands, the memory to expand, external interrupt expansion.
1.1 SFR expansions
For and MCS51 is compatible. In FSK, DTMF control register and condition register MCS51 SFR unified address. When such 8051 management, the control, monitor FSK, DTMF, may FSK, the DTMF correspondence address regard as is the internal data-carrier storage’s one-level address. Therefore, may use the internal data-carrier storage same operating procedure, does not need to increase the instruction to complete these functions, this kind of structure’s expansion may regard as is the MCS51 interior main line’s expansion and FSK, DTMF regards as MCS51 two expansion internal modules, structure as shown in Figure 1.
1.2 memories expand
Because the solid net system needs huge fonts to support, therefore the MCS51 64KB memory property is insufficient. Through increases a MMU module, should save ability CPU to expand 2MB. When CPU visits the exterior memory, uses 16 logical address top digit to carry on the page table first to inquire, obtains the corresponding extended address, then the extended address and logical address’s low position will constitute 21 physical addresses together, will complete to the exterior memory’s operation, data path as shown in Figure 2.
1.3 external interrupt expansions
In order to enable the system the old electricity breakdown and so on unusual event interrupt request signal, retained the MCS51 original two exterior interrupt source, simultaneously increased 7 external interrupt and the corresponding 3 registers, uses in the lock saving the interrupt, the shield interrupt and carries on the control to the interrupt priority separately. As shown in Figure 3.
Interrupt realization, CPU inspects each interrupt source in each machine cycle pre-foreword, if discovered that has the interrupt request, and not in processing same or higher priority interrupt, CPU processes this interrupt. The corresponding priority status byte setting, then picks up a hardware subroutine first. This subroutine delivers interrupt handling routine’s entry point address the procedure to count the data. Each interrupt source program’s entry point address like table 1. interrupt handling routine starts from this address to carry out until the RETI instruction, then corresponding priority level clear 0.
Table 1 interrupt service entry point address
| Interrupt name | Interrupt entrance |
| Fsk receive interrupt | 002B |
| Cas interrupt | 003B |
| Fsk transmission interrupt | 003B |
| Reversal of poles interrupt | 0043 |
| Picks machine the interrupt | 004B |
| Gating clock interrupt | 0053 |
| Watch-dog interrupt | 005B |
2 DTMF data processing
The DTMF decoding data processing mainly completes two functions; first, data interception; first, DTMG decoding.
2.1 data interceptions
According to the sampling speed and the DTMG dutyfactor and the duration, may carry on the interruption to the receive data. According to the FFT request, around between two sections of data should have the certain length common segment. Calculates the truncation recent data frame the length is 128 characters. In order to reduce the area, we have compared several plans. Will not present the overflow in the situation, finally has adopted the design proposal which shown in Figure 4.
Figure 3
The data interception completes by 256 character’s pair of mouth RAM. When replacement, to first 32 character reset. A/D sampling’s data frame puts first to writes the data segment in 1, then puts to writes the data segment in 2, according to writes the data segment 1 and writes the data segment 2 alternately write data. After each time finished a data segment, produces a data change pulse. Uses for to indicate already completes 1 data, may carry on the data read, thus log-on data read operation.
When data read, to guarantee each time when data read and around two sections both have 32 character common segments, first time from reads the data segment in 1 to read out 160 characters the data, its first 32 character data for previous data finally 32 character data; Next time in reads the data segment in 2 to read out 160 characters the data, then around two data segment readout between some 32 characters altogether have the data.
2.2 DTMF decodings
FFT which uses regarding the DTMF decoding, we use the classics the Goertzel algorithm. Its thought is the use simple recursive operation replaces the complex FFT operation, and only needs the value which calculates several frequencies to occupy, simplified the computation load greatly, through compares several frequencies to light the value the size and the judgment accounts for the spatial time, may determine the transmission the DTMG group frequency. In order to reduce the multiplication confirmation which in the design uses, in satisfies the correspondence standard under the premise, falls the width to 12. The Goertzel algorithm’s formula is as follows:
3 other peripheral circuits
This system besides MCS51.FSK, DTMG, in addition gating clock. The watch-dog, the digital modulation/demodulation and so on other electric circuits constituted completely take MCS51 as the nucleus monolithic integrative systems.
The gating clock major function is when the system work provides the system clock; When systematic free time, under causes the system to be at the electricity condition, all clocks switch off, all operations also stop, is awakened until the system, like this reduces the system power loss the minimum value.
Guards the door the electric circuit is a programmable logic circuit, it may serve as the system monitoring device, may also only take a simple timer. Simultaneously its time width may suppose 2 12, 2 13, 2 18 or 2 21 clock widths through the programming.
Conclusion
This system is one typical take MCS51 as a core. Peripheral circuits and so on Canada, DTMG as well as gating clock compose control system. We use the design method from the top. In the system all functional module uses the VHDL language to carry on the description; The integrative system replace original system which realizes with FPGA passed the function testing. Not only had the enhancement in the reliability, moreover satisfies the chip area the request, achieves reduces the cost the goal.
