Abstract: Gave has taken the core processor by two piece of high performance TMS320C6414, and auxiliary realized the system logic sequential control by FPGA, thus the group formed a pair the DSP flexibility aircraft-borne real-time imagery processing system’s design proposal. Meanwhile has carried on the discussion to system’s hardware source choice and the work flow.
Key word: DSP; Parallel processing; FPGA; Flexibility; Supervelocity
1 introduction
Realize the real-time goal image formation track using the visible light image formation and the infrared image-forming sensors are the precision guided munitions and the aircraft-borne image formation electro-optic system research core technologies. Follows the actual combat environment to be day by day complex as well as target characteristic control technology and so on camouflage, stealth swift developments, the aircraft-borne real-time image tracking system’s application day by day is also widespread and is thorough. When tracking object by no means general ground idling speed goal, but will be other fast-moving target 熑 relieves dry Tu Zhan jealous, the pilotless plane and so on 犑 to guarantee the system to request the existing aircraft-borne real-time image tracking system to have the higher technical performance. Based on this, to further enhance the existing aircraft-borne photoelectric follow-up in the actual combat environment, in view of the complex scene under fast-moving target implementation real-time track’s robustness and the stability, the author proposed that as the core constructs take double DSP and FP-GA main from the type supervelocity parallel processing system’s design concept, and studied has developed based on the double DSP new flexible aircraft-borne real-time image tracking system. At the same time, uses the double DSP architecture to realize the system task parallel division to cause this system to have the extremely high operation processing speed; On the other hand, the scene programmable logic component FPGA introduction enables system’s flexibility also to have the enormous enhancement. But may cause both union this system to manifest the new generation aircraft-borne real-time image tracking system to be faster, to be more precise fully, a more nimble characteristic.
Figure 1
2 TMS320C6414 unique features
The US Texas Instruments Company (TI) promotes new generation digital signal processor TMS320C6414 (hereafter refers to as C6414) the basic frequency is 400MHz~700MHz, its data-handling capacity is 3200MIPS~5760MIPS. This component’s structure diagram as shown in Figure 1. Its main feature is as follows:
(1) the DSP essence uses the ultra long instruction word (VLIW) the architecture, some 8 function unit, 64 32bit general registers, a clock cycle may simultaneously carry out 8 instructions, the operational capability may achieve 5760MIPS;
(2) to enable the data to satisfy the supervelocity DSP essence the demand, C6414 has used two level of supervelocity buffer storages, namely 16k Byte first-level data Cache, 16k Byte first-level procedure Cache and 1024k Byte data and procedure unified memory.
(3) increased the direct processing pack data command, may establish the seamless data stream, enhances the set of instructions the efficiency;
(4) each function unit increased the additional function on the hardware, thus strengthened the set of instructions orthogonality.
3 system hardware designs
This electro-optical image formation tracking system hardware platform is composed of six parts: Image gathering and pretreatment module, sync split module, FPGA logical control module, double DSP pair of mouth RAM imagery processing module, asynchronous communication module and graphical display module. Its system principle diagram like 2 show. May know from Figure 2: The infrared acquisition aid and the visible light photograph meter outputs the simulated video signal inducts after the multi-channel signal choice chip, after clamp, enlargement, filter as well as desynchronizing prime pretreatment, as soon as will go via a/D switch the simulated video transformation will be the 8bit digital signal and inducts outside the piece the video frequency buffer 1, 2, will then wait for FPGA the sequential control DSP external interrupt, in order to the complete buffer data removal to the DSP internal 2 levels of buffers, will realize again through the system task division the data reorganization, will then carry on synchronized parallel data processing separately in the host from DSP, and by will advocate the intermediate result the DSP synthesis, finally after completing the following operation will give matches the result finally. Meanwhile, advocates DSP through to write the graphical display buffer to match the goal the positional information to transmit the outside; Another group simulated signal forerunner enters the synchronized separator, then withdraws the good field synchronizing signal to deliver FPGA to take the time base, produces the system all levels of sequential control signal; The third group simulated signal gives the graph superimposition electric circuit to take one of input superposed signals, the regulation when arrives on the scene, the FPGA interrupt control and reads out the graph memory data, simultaneously internal realizes the read-in data in FPGA and/the string transformation backward shift output to the graph superimposition electric circuit, this time two groups signals send in the juncture the video frequency monitoring device, thus completes on the video image the graph demonstration. Overall system duration of work, every other 80ms advocates DSP also to carry on the serial communication through the asynchronous transceiver with the exterior superior machine, so that the system can the real-time receive external command and the target component 熃 adjusts tracking system’s active status.
3.1 image gathering and pretreatment module
In this system’s multi-channel choice component selects the CD4052 chip. It can act according to the different work situation to cut the infrared/visible light video input; The video frequency pretreatment electric circuit uses AD817 to carry on the video signal the enlargement, by obtains a clearer signal to carry on the video processing; A/D chip selects AD Corporation’s AD9225, the output 8bit digital video signal sends in 74LS245 to carry on the data lock to save.
3.2 sync split module
The system uses section of special video frequency synchronization separator LM1881 to come from standard negative synchronized NTSC (PAL or SECAM) in the video signal separates the effective line/field synchronizing signal, and sends in it FPGA to produce system’s all levels of logical control output.
3.3 FPGA logical control module
Because in the system each chip’s function relative independence, needs to coordinate these chips the operation 熅 to hold a chessboard piece of control logic function the programmable chip, for this reason, the author has selected ALTERAL Corporation’s EPF10K30A, this chip has 246 user I/O mouth, 30000 typical gates, 216 logical array block, 1728 logical unit 煵 to call Ju Lizu system’s control request, moreover may also provide the control logic for the future system’s function expansion. In this photoelectric follow-up, FPGA mainly uses for to complete the following several aspects the work:
(1) produces a/D sampling control clock, realizes the simulated video correct sampling;
(2) provides the character graph memory address and selects patches or strips of land as worth saving for seed/reads the control signal, when and regulation arrival on the scene, control graphic data read-out;
(3) provides the video data buffer storage address and selects patches or strips of land as worth saving for seed/writes the control signal, control video data continual read-in;
(4) has the external interrupt 4 to double DSP, when the data writes all over the video image high speed buffer predetermined space, controls main from DSP by the block data fast removal to the internal 2 levels of buffers;
(5) has the external interrupt 7 to advocate DSP, and when each field counter regulation time arrives, the control advocates DSP to scratch, to write the character graph memory data;
(6) produces one and/the string switching circuit, by parallel read-in character graphic data serial shift output to graph superimposition electric circuit, thus realizes ” “, “□” the graph on video image superimposition.
Its FPGA internal structure diagram as shown in Figure 3.
3.4 pair of DSP pair of mouth RAM imagery processing module
The high speed parallel digital signal processing electric circuit take double DSP as the concurrent operation processing core unit, and auxiliary realizes the video image high speed buffer by pair of mouth RAM, thus completes the big operand the high speed real-time target tracking processing duty. This parallel processing system’s composition and the function minute states as follows:
a. Video image high speed buffer submodule
In order to realize image real-time gathering and high speed processing, this system with two piece of pair of mouth RAM composition independent video frequency buffer, corresponds separately mutually main/from the DSP processor. When design selects IDT Corporation’s 3.3V asynchronous pair of mouth PRAM IDT70V657, simultaneously selects the ASRAM method with the DSP connection. Because the EMIF ASRAM connection supports 32Bit the data interface, therefore, deposits and withdraws the data using the IDT70V657 constitution incomplete address structure to be able to realize the 8Bit lock to save the data and the C6414 connection well, but does not need to DPRAM to carry on the width expansion. Simultaneously may also reduce DSP to read the exterior data the time expenses.
The IDT70V657 size is 32K×36Bit 熛 the low nest takes intermediary two DPRAM to divide respectively for the around two half-court ways realizes time the deposit data pingpong cut. Namely in system work any one time, when to DPRAM first half write data, causes the DPRAM second half to the DSP readout. When current half-court writes all over the video data, sends out the signal of stop by FPGA to DSP, informs DSP to read out the DPRAM the first half place write data, simultaneously, reads in a/D switch’s data the DPRAM second half buffer space, carries on so repeatedly realizes the data read-out with to read in the synchronous operation.
b. Double DSP high speed signal processing system
The TMS320C6414-600 DSP basic frequency reaches as high as 600MHz, has the very splendid performance in the supervelocity real-time imagery processing domain. This system’s double DSP high speed real-time signal processing system take 2 piece of C6414-600 the DSP chip as the core composition neighborhood image parallel processor, and realizes synchronized concurrent operation processing through system task’s division and the decomposition. Its system diagram as shown in Figure 4.
In this system, advocates the major function which DSP completes to be as follows:
(1) realizes exterior buffer data to the internal removal, is the DSP high speed batch run opens the internal second-level buffer;
(2) realizes with the exterior superior machine immediate communication, receives the external command and the target component;
(3) realizes with from the DSP immediate correspondence, the downloading order character and the target component as well as the gain intermediate result;
(4) the run-time system track algorithm, undertakes system core operation duty half;
(5) establishes the immediate correspondence with FPGA, realizes the system program module dispatch and the coordination;
The major function which completes from DSP is:
(1) realizes the exterior buffer data to the internal removal, is the DSP high speed batch run opens the internal second-level buffer;
(2) the run-time system track algorithm, undertakes system core operation duty half;
(3) realizes with advocates the DSP immediate correspondence, the upload match operation intermediate result;
(4) establishes the immediate correspondence with FPGA, realizes the system program module dispatch and the coordination.
The double DSP processing system’s flexible characteristic manifests in: May rest on the real-time requirements of environment to load the different track algorithm to realize the target tracking. At the beginning of the algorithm movement, two piece of C6414-600 both under the FPGA control, through the EMIFA mouth by the EDMA way, divides certain time, decides 牻 in the exterior video frequency buffer data according to the system trace algorithm (an image) to read in DSP in turn in the L2 internal buffer; After algorithm movement, main directly interlocks from DSP through McBSP realizes during double DSP high speed synchronous communication 熞 to come to realize trades the emperor according to the processing result.
In the system design, Flash ROM selects AMD Corporation’s AM29LV800 (1M×8Bit) to come FLASH to map DSP unification address address space EMIFB the mouth the CE1 space. When on after system electricity replacement, this address space to the first guidance field, then like the application procedure code load to the internal high speed execution, thus realizes system’s off-line movement.
3.5 asynchronous communication modules
This system mainly passes with the exterior superior’s machine asynchronous communication advocates DSP McBSP. C6000 McBSP is a function very formidable standard serial port, supports the full-duplex serial communication, its double cushion data register permission continual data stream, may with reach 128 channels to carry on the receiving and dispatching correspondence much. Through to McBSP SPCR, RCR, XCR, SRGR, the PCR register’s disposition may realize when the system communication receives and dispatches the data the frame synchronization and the clock synchronization.
Because exterior superior’s machine communication mechanism is the RS422 standard, but DSP only provides the RS232 connection with the external communication, therefore should use a piece of MAX3074 chip to realize RS422 to the RS232 transformation.
MAX3074 is one section which MAXIM Corporation produces uses in RS422/485 specially to the RS232 transfer chip, uses the 3.3V power supply, this periphery power line voltage is consistent with C6000 the DSP, the connection is convenient, no longer needs the unnecessary voltage adapter. On the other hand, because McBSP is the synchronized serial port, to realize McBSP and the RS232 seamless connection, may join the transmission expansion algorithm and the receive compression algorithm through the software, thus realizes DSP and the superior machine asynchronous serial port communication protocol handshake.
3.6 graphical display module
This module by the graph memory, the graph superimposition electric circuit and the video frequency monitoring device is composed. The graph memory chooses IDT Corporation’s 70V08 (64K×8Bits) DPRAM to save the marking goal to match the position the graphic data. The graph superimposition electric circuit uses in realizing the video frequency and the graph superimposition, and demonstrates the superimposition result finally by the video frequency monitoring device.
4 system work flow
This system’s software work pattern including the replacement and the initialization pattern, the movement pattern, the system maintenance pattern, may control three kind of patterns by the system program the cuts.
In repositions and under the initialization pattern, after system initiation, will realize the procedure removal by the host from the DSP synchronization, procedure code removal to internal and run-time system procedure, thus the initialization main and establishes the related parameter from the DSP movement environment.
Under the movement pattern, double DSP responds and processes the FPGA interrupt, the movement core track algorithm independently at the same time and realizes in subsystem’s process dispatching; On the other hand as well as advocates DSP serial port and long-distance main engine’s functions and so on communication through host’s from DSP serial port between interconnection response of interrupt realizes process dispatching between the double DSP subsystem and the double DSP system and the exterior main engine’s.
Under the system maintenance pattern, main from DSP after carrying on the system self-check, may by the long-distance main engine through the RS422 connection with advocate DSP to carry on the communication, realizes functions and so on procedure renewal downloading and parameter revision. Figure 5 is the system software work flow diagram.
5 concluding remark
The author carried on the simulation test to this system’s timeliness, the result analysis had indicated:
(1) list DSP can only realize the windowing search, once under the high speed situation the goal escape search sector, will cause the track rejection; But this system can realize based on the entire field search big operand processes high speed, thus has enlarged by the tracking object search sector dynamirange, has avoided the track rejection situation occurrence, further enhanced the real-time track reliability.
(2) the traditional list DSP system can only realize generally based on a match performance, but this system may realize based on chases the field the track match, further enhanced tracking system’s timeliness.
(3) according to the actual situation’s need, this system may through the software choice load track algorithm, thus the enormous enhancement system’s versatility and the easy maintenance, to manifest the flexibility processing system’s characteristic.
Thus it can be seen, the double DSP flexibility processing system the rapid traverse goal’s high speed recognition and the track provided one for the complex scene under effectively to realize the plan, simultaneously has also provided the new high speed processing platform for the aircraft-borne real-time image tracking system.
