Abstract: Introduction based on Altera on Excalibur platform light signal gathering piece systematic design, analyzes on detail the piece the system each constituent principle of work. As a new measurement system, it has nimbly, characteristics and so on stable, high efficiency.
Key word: On the piece the system fiber grating light signal gathers Nios
Introduction
An item has the prospects for development new technology - fiberoptics and the fiber grating very much (FBG, Fiber Bragg Grating) the technology, was already applied in the temperature and the deformation online survey. The FBG sensor’s characteristic has the good stability, the reliability. In addition, it also has based on optical fiber sensor’s some altogether has the merit, like to the electromagnetism immunity, the size is small, the sensor and between the data gain installment the distance may be very far; Can therefore overcome traditional the temperature and the deformation sensor (for example thermo-element and deformation measuring instrument) many shortcomings, like weight, degree of hardness aspect flaw as well as to environmental variation disturbance resistance difference and so on.
This article mainly introduced that to the FBG sensor signal’s fast gain method, introduced with emphasis based on FPGA Altera Corporation’s Excalibur development board, designs on a piece the embedded measurement system, gains the light signal with it. With present has the similar function other measurement system to compare, it has nimbly, stable, easy to maintain, merits and so on high efficiency. This measurement system’s hardware development includes, uses Altera the Excalibur development board disposition to produce one to inlay has the Nios processor “on the piece” the measurement system, as well as uses CCD and high speed ADC designs the electro-optical signal the transformation and the gathering electric circuit; The software development includes, succession signal’s Verilog realizes in Apex EP20K FPGA, uses the C language to the electro-optical signal gain.
1 system structure
The measurement system is composed of the following several parts: The optical system, the laying aside are measured in the object the fiber grating (FBG) and the signal gathering processing part. In which optical system including the photo source and the spectrometer, the use high luminance’s laser generator takes the photo source, uses in producing the incidence to measure in the object optical fiber’s light wave. Its power is bigger than 1mW, 
the light frequency spectrum is located at 808~858nm, after the incidence, some wave length light wave by the diffraction grating is reflected, and enters the spectrometer. The spectrometer is composed of certain reflectors and the holographic grating, the leading role is carries on the photo processing after the light wave, enables the light wave accurately to project on CCD, transforms the electrical signal the light signal, is advantageous for the signal gathering and processing. In the system the signal gathering processing part is switch as well as Altera the ExCalibur development board is composed of CCD the line row sensor ADC. Its function is projects the light signal becomes first on CCD simulates the electrical signal, then again transforms through ADC the signal the digital quantity signal, then through Altera’s in the Excalibur development board’s piece the Nios embedded system, carries on gathering and processing to these digital quantity signal, obtains the corresponding temperature value and the strain value, with the aim of completing the entire measuring process. System frame schematic drawing as shown in Figure 1.
2 fiber gratings (FBG) sensor principle of work
The fiber grating (FBG) the sensor is the optical fiber sensor’s one kind. It not only may use in the static signal, but may also use in the dynamic signal gathering, for example temperature, deformation and pressure and so on.
Following union chart 2 introduction fiber grating (FBG) principle of work.
The fiber grating (FBG) sensor’s principle of work is with some wave length light signal expressed that we hoped gathers physical quantity. In optical fiber’s diffraction grating may regard as is “the filter”. According to diffraction grating’s physical property, enters optical fiber’s light wave some wave length part to reflect by the diffraction grating, this wave length’s light wave from enters in body’s light wave “the filtration”. Thus, we hoped gathers the physical quantity “the modulation” has become this wave length light signal on the quilt.
Figure 3 cushion interface circuit
The supposition diffraction grating’s reflection factor is neff, between the diffraction grating geometry distance is dB, obtains through the following formula the light wave length which reflects λB=2×neff×dB. The mechanical stress will change between the diffraction grating the geometry distance, but the temperature change will change the diffraction grating the reflection factor. May consider, in known temperature T0 and under the known pressure ε0 condition, the reflection wave length for λB0, that may ε1 corresponds the reflection wave length through examination unknown temperature T1 and the unknown stress λ1 and λB0 between wave length displacement, calculates obtains temperature T1 and the stress at this moment ε1, the formula is as follows:
And diffraction grating related often coefficient c1, c2, decided by the diffraction grating calibration process.
Stress ε1= (λ1-λB0)/[(1-Peff)] ×λB0
And the diffraction grating often coefficient Peff is the diffraction grating light models often the coefficient.
3 CCD image sensor’s choice
For the convenience system carries on processing to the FBG output’s light signal, must transform it the electrical signal, we use the electro-optic signal shifter not to complete this aspect the work. In this system, because the illumination source’s spectrum scope is 808~858nm, therefore we have selected the spectrum scope are the 200~1100nm 2048 picture element gradation lines arrange in order CCD image sensor ILX511B.
CCD transforms the light signal simulates the electrical signal, each picture element produces a simulation electrical signal, such CCD each time carries on the electro-optic to transform produces 2048 simulation electrical signals; At the same time, it serial “the seal” becomes these 2048 picture element position a valid data field, may, in the sur- clock synchronized signal (CLK) and the chip causes to read the end (ROG) under the function, from CCD readout. The sur- synchronized clock signal is composed of 2087 clock pulses, under each clock pulse function, a data position is read out. These 2087 data position is composed of the following several parts: First false data field (33 data positions), valid data field (2048 data positions), rear part false data field (6 data positions). What needs to pay attention, to enhance the electromagnetic compatibility, as soon as the CCD working should choose for the sampling maintains a way; At the same time, CCD after on electricity is at the internal circuit initialization stage, to avoid obtaining the wrong data, at first 22 500 clock pulses use in initialization CCD, do not in this stage readout.
4 ADC connection design and Altera Nios platform
4.1 ADC connection design
Transforms the output after the CCD sensor the simulation quantity, must transform the digital signal through the ADC switch, such system only then may process these signals. Because the CCD dynamirange is 48.5dB, according to formula
ADC precision >= dynamirange (dB) /20×log2
May calculate obtains the ADC precision ≥8.06, therefore chooses ADC the precision to be 9 or above 9; At the same time, calculates ADC according to the following formula the speed:
fs=1×2MHz (the CCD biggest clock rate) =2MHz (sampling and maintains way).
Through the above computation and the analysis, obtain need ADC two principal characteristic target, namely the precision takes 9, the sampling speed to at least at least 2Msps.
Now, has many ADC switches to be possible to apply in the CCD imagery processing. After overall evaluation many factors, we choose Linear serial ADCLTC1402.
When designs the ADC interface circuit, below must pay attention to some questions. First, because the LTC1402 interior input signal “maintains - the sampling” electric circuit’s speed achieves 80MHz, therefore, the exterior noise and the disturbance may have the influence through the LTC1402 input end to a/D transformation. According to the LTC1402 data book’s request, the method which we solve is, adds on the first-order filter circuit in the LTC1402 input end, input signal frequency restriction in certain scope. Next, the CCD output is quite sensitive regarding the outside impedance change, if ADC input end and CCD output direct connected, then the CCD load possibly changes along with the ADC input end interior impedance’s change. Based on the above two considerations, we have designed the cushion circuit between CCD and ADC, uses in the impedance matching and the filter. Cushion interface circuit as shown in Figure 3.
May calculate ADC by Figure 3 the input upper frequency:
fg=1/[(2× π×R5×C3)]=10.3MHz.
4.2 Altera Nios platform
After careful analysis system’s characteristic, we decided that chooses aims at SOPC application specially Altera the Excalibur development suite. Development suite including the below part:
*Nios processor as well as periphery connection;
*Quartus II develops the software;
*GNDUro compiler;
* based on APEX EP20K200E FPGA development board;
* related development routine.
Figure 5 clock and control signal generator simulation succession
We use the integration tool to dispose in QuartusII SOPC the Builder live on the Large expanse of system. SOPC Builder is a function formidable the systematic definition and has custom-made the tool based in the graphical interface piece, may complete the SOPC design which in a short time the user has custom-made. According to the application need, storehouse chooses the IP module, the memory, the periphery connection and the processor from SOPC in the Builder, and disposes produces a high integration rate the SOPC system, thus below selects on some module group Large expanse of system: Nios 32bit CPU, Boot Monitor ROM, Communication UART, debugging UART, Timer, Button PIO, User PIO, LCD PIO, LED PIO, DMA, SPI, Seven Segment PIO, External RAM Bus (Avalon TriState Bridge), External RAM Interface, External Flash Interface.
At the same time, SOPC Builder has some essential arbitration logic to come in automatically the coordination system above each part’s work, we the systematic operating frequency will suppose will be 33MHz. After having custom-made on the piece system’s hardware, SOPC Builder also operated these piece on hardware’s software code for the compilation to provide a software development environment, this software environment including a language document, the periphery connection’s actuation as well as real-time operating system’s essence, has facilitated software’s development enormously.
5 systems realize
The following is divided two parts to analyze and to introduce:①In ApexEP20K FPGA, uses the Verilog compilation clock and the control signal generator uses in actuating CCD and ADC, and is coordinated both the work;②Uses the C language write program, connection reads the ADC output through SOPC Builder the disposition SPI the data.
5.1 clocks and control signal generator
Uses the Verilog compilation clock and the control signal generator, uses in producing actuates CCD and the ADC clock and the control signal. The clock generator’s principle of work is: The frequency of use is the 33MHz system clock, sells as the clock generator’s input and the synchronization, uses in CCD which and the ADC actuation clock and the control signal produces needs. According to system’s request and CCD as well as the ADC chip characteristic, the CCD clock rate which will produce supposes is 1MHz; Meanwhile supposes the ADC clock rate is 33MHz. In clock generator, but also needs pair process CCD and the ADC two high-speed equipment’s clocks and the control signal carries on the match, enables both to be able to work normally.
How now analyzes these two high-speed equipments to complete the succession in detail the match. Because in system’s CCD and ADC are the dependence sur- clock synchronization high-speed equipments, therefore, whether between these two equipment’s succession’s match regarding did gain the correct effective data very important. In order to cause two equipment joint operation, must first analyze the sur- clock which each equipment needs and control two sur- signals, respectively is CCD_ROG and CCD_CLK. The CCD_ROG signal causes CCD the output data to be effective, when is each time from the CCD read data, must give a CCD_ROG low level first, sets at the electro-optic transforms a data place output after CCD. ADC carries on a/d conversion also to need two sur- signals, respectively is ADC_CONV and ADC_CLK. The ADC_CONV signal makes the ADC chip to start to carry on a/d conversion, before each time carries on the transformation, to give a ADC_CONV high level; At the same time, after the switching process and the transformation result output completes in the ADC_CLK signal’s synchronization.
Because needs first from the CCD electro-optic switch read-out analog data, therefore, must pass CCD_ROG to a CCD length is t1(t1=4000ns) low level. After CCD_ROG becomes the high level, CCD under the CCD_CLK signal’s synchronization the output data, has output a simulation quantity data under each CCD_CLK function. CCD each time outputs 2087 simulation quantities separately by 33 first false data fields, 2048 valid data and 6 rear part false data field are composed. In which 2048 valid data and the first false data field’s latter 20 data are we hopes to obtain, therefore from the 14th data to the 2081st data’s in each simulation quantity, through ADC_CONV (the ADC_CONV high level width is 4ns), gives a high level to start ADC; At the same time, under the ADC_CLK function, completes a/d conversion process and the digital quantity output. Figure 4, chart 5 is the clock and the control signal generator procedure flow and the simulation succession chart.
5.2 SPI connection programming
After ADC the simulated signal will transform the digital signal, Nios reads in these signals through the SPI connection and carries on corresponding processing. We are the Nios nucleus dispose the SPI connection through Quartus II SOPC Builder. In ours system, the SPI disposition for from equipment. Software 5 16 registers which maps through the reference to storage in control and the read-write SPI connection. The read-in data enters the shift register through the MOSI pin by the position. After shift register’s shifting and cushion, a data enters register rxdata, simultaneously the condition register’s rrdy position 1, through visits rxdata to obtain a data. After the data reads, the rrdy position automatically sets 0. If the preceding data from the rxdata read, the latter data the original data cover, will not have created the mistake, simultaneously (Read Overwrite Error) the position will become condition register’s ROE 1. The SPI connection altogether has 4 pins, respectively is MISO (Master Input Slave Output), MOSI (Master Output Slave Input), SCLK (synchronized clock) and SS_n. When SS_n is the low level, may read in the data from the equipment under the SCLK synchronization. In system’s SPI connection is from the equipment, therefore only uses MOSI, SCLK and the SS_n three pins. Figure 6 is in Nios SPI and the ADC connection schematic drawing.
May know from the ADS chip characteristic, when ADC_CONV under a high level’s function, ADC starts to carry on a/d conversion. After ADC_CONV replies the level, because of SS_n and ADC_CONV continually in the same place, therefore in Nios SPI was at may read in the data the condition; At the same time, under ADC_SCK function ADC output data, but SPI also under same clock SCLK function, through MOSI read-in data. For can obtain the data accurately, but must figure suppose SPI the register rxdata is 13. In the software, we through will wait for that SPI register’s rrdy position’s setting, reads in rxdata the data, at the same time in the register the roe condition decided that this data in read process whether to have the data overflow phenomenon. The following is the related read data software code.
do {
// reads a line of CCD data
for (i=0; i<2069; i ) {
// waited for, until prepares
while(spi->np_spistatus&np_spistatus_rrdy_mask)==0)
;
// reads the data from the SPI data register
c[i]=spi->np_spirxdata;
}
// reads the cover condition
b=spi->np_spistatus&np_spistatus_roe_mask;
} while(b==8);
Conclusion
This system after the simulation test, its function has achieved the design requirements, and has confirmed the system function with the HP logic analyzer.
