Abstract: In the article introduced ATMEL Corporation’s high performance AVR the monolithic integrated circuit ATmega103 main performance characteristic, has given ATmega103 in the FH frequency-hopping system digital signal processing module application method, introduced in detail the internal synchronized serial port SPI use skill, has simultaneously given the SPI communication application procedure.
Key word: Monolithic integrated circuit; Frequency-hopping; SPI; Digital signal processing; ATmega103
The ATmega103 monolithic integrated circuit is the simplification set of instructions which ATMEL Corporation promotes (RISC) AVR (ADVANCE RISC) the series monolithic integrated circuit product, this is one kind of enlargement mode RISC structure, used the CMOS technology 8 micro controller 煾 intermediary loess hill drum yi line еС to refer to m the team americium to pound the approximately regretful xiang enormous assembler code procedure.
The frequency-hopping system (FH) is refers to the carrier frequency according to some kind of frequency-hopping design (frequency-hopping sequence) the communications system which jumps in the very wide frequency band scope, because this system has the antijamming, the anti-multi-diameters and abilities and so on anti-fading, therefore obtained the widespread application in military and the civil domain. In this system plan, the signal processing module mainly completes the frequency-hopping pattern (FH) under related digital signal processing, arranges the decoding, the voice organization and with the synchronized related operation including the voice and so on, these technologies are one at present frequency-hopping system’s key technologies.
This article introduced that simultaneously the ATmega103 monolithic integrated circuit’s characteristic and in the FH system digital signal processing module’s application method, introduces SPI in detail (Serial Peripheral Interface) the characteristic and the application.
1 ATmega103 monolithic integrated circuit outline
ATmega103 is based on AVR RISC structure 8-bit the low power loss CMOS microprocessor, it has absorbed the PIC series and 8051 series monolithic integrated circuit’s merit, and has made the major improvement, its characteristic is as follows:
* the power line voltage is 2.7~6V, the basic frequency is highest may reach 12MHz;
* has 120 instructions, majority instruction time for single clock cycle;
* has the Flash memory which the 128k byte internal may download (SPI serial to download 1000 time life) and 4k byte internal RAM as well as 4k byte internal EEPROM;
* has 32 programmable I/O lines, 8 input lines and 8 output lines;
* has 32 8 general registers;
* contains 2 8 timers and 1 16 timers;
* has the programmable serial UART SPI connection;
* has the internal interrupt source and 8 exterior interrupt source;
* has 8 channel 10 electric circuits and so on A/D switches, internal simulation comparator as well as watch-dog;
* may the online programming.
Because ATmega103 its above characteristic causes it to become one kind to suit in multi-purpose, fast, and has highly flexible and the high performance-to-price ratio micro controller.
2 frequency-hopping signal processing to monolithic integrated circuit’s request
The frequency-hopping signal processing module is one of FH broadcasting station’s essential parts, mainly uses in completing duties and so on broadcasting station’s synchronization and related data processing organization. The monolithic integrated circuit is this module core, module many functions is direct or under the indirect participation completes in the monolithic integrated circuit. The overall evaluation, monolithic integrated circuit’s is approximately as follows in this module function:
(1) completes the mass data exchange, because broadcasting station in work time needs to receive or the transmission massive other monolithic integrated circuits as well as the module interior related parameter data;
(2) completes the fast real-time processing function, because the module processes immediately to many information requirements, for example TOD (Time of Day) information, voice data, real time operation frequency computation and so on.
(3) uses in the data exchange, including monolithic integrated circuit connection, TOD, synchronizing information, control state parameter data interface and so on.
(4) completes the massive operations. Generally broadcasting station when FH working, jumps every time needs to calculate TOD, the operating frequency, the receive or the transmission data organization again.
(5) provides many kinds of control state line through the enough I/O mouth, supplies the broadcasting station and the module interior use.
(6) comes the massive middle data which through the internal mass data in the memory block deposit operation process produces.
3 design mentalities
According to broadcasting station FH signal processing module to monolithic integrated circuit’s request, if selects the 89C5X series monolithic integrated circuit, not only in realizes in the function to be quite difficult (for example operating speed, I/O mouth quantity and so on), moreover needs the periphery expander must increase (for example RAM, passes unguardedly and so on). But selects the ATmega103 monolithic integrated circuit to be able to satisfy the design requirements well, therefore, this design selects the ATmega103 monolithic integrated circuit to realize the signal processing module function. Shown in Figure 1 is its hardware schematic diagram.
In addition, in actual use, but must pay attention to the software design. For ease of the debugging, the maintenance and the function expand, this system uses the modularized program design proposal; Moreover considers software’s reliability, but also increased fault-tolerant and the redundancy design; At the same time, in view of data interface many characteristics, in the procedure has also designed concisely, the versatile connection communication protocol.
4 Atmega103 SPI in FH application
May know by the above description, SPI holds the important status in the design, the module interior primary control and the data exchange completes by it, below introduces SPI in detail in the module design method.
4.1 SPI principles of work
Between ATmega103 and the peripheral device may carry on the high speed synchro data transmission through SPI. Main receives shown in Figure from the CPU SPI company 2. And, SCK is main engine’s clock outputs with from machine the clock input. Will read in the main engine SPI data register’s operation the data to start the SPI clock producer, this time, the data from main engine’s MOSI emigration, and high machine MOSI will move, after moving to a byte, the SPI clock stops, and established the transmission end mark. This time if SPCR SPIE (the SPI interrupt enables) the setting, then initiation interrupt. Chooses some component for from the machine-hour, may pull lowly from machine choice input end SS. Main from machine the shift register may regard as is a distributional 16 end around shift register. When the data carries over from the main engine from machine at the same time, the data will be also high machine carries over the main engine, thus realizes in the shifting process main from machine data exchange.
SPI main register including control register SPCR, condition register SPSR, data register SPDR. And SPCR uses in establishing SPI the interrupt to enable, the data transmission order, the host from machine the choice, the clock phase and the clock rate and so on; SPSR is the SPI interrupt symbol, uses in symbolizing that writes the conflict. The SPDR register uses in the register file and between the SPI shift register transmits the data. When writes this register, will carry on the initialization first to the data transfer, when reads this register, will read will be the shift register receive buffer value.
4.2 SPI programmings
In this FH signal processing module, monolithic integrated circuit through SPI and FPGA exchange data. FPGA selects Xinlix Corporation’s XCV100. Below introduces several main subroutines specifically:
(1) SPI initialization
Procedure when replacement, usually must carry on the initialization to the SPI mouth. If the monolithic integrated circuit establishment is a main engine. The SPI data order is the LSB 煹 buttocks fools 犜 sui # cherry vast peak my to well up bonds shades the low level awake, in SCK drop along sampled data; The clock is the system clock 1/128. , The concrete initialization routine is so as follows:
reset:ldi rx,$0
out spsr, rx; The clear SPI interrupt symbol, writes the conflict symbol
ldi rx,$0f7;
out spcr, rx; Establishes SPI the transmission parameter
(2) SPI calling order
The monolithic integrated circuit each time needs to give the 10byte related code FPGA, therefore should SRAM the area $09c2-$09df section hypothesis be the SPI data buffer, then took the data by SPI from this buffer until end of transmission. The SPI transmission function is as follows:
spi_send:ldi xh,$9
ldi xl,$0c2;
sts spififoo, xl; Supposes the SPI buffer’s output address is $c2
ldi ry, 10; Stores the address which the 10byte related code $9c2 starts
s67_2: ld rx, y ; y is the related code depositing address
st x , rx
s67_3: dec ry
brne s67_2
sts spififoi, xl; Stores spififoi the SPI buffer’s entry address
ldi rx,$0aa; Will send the related code symbol $aa to pass SPI
out spdr, rx; Gives FPGA
sei; Opens the interrupt
ret
(3) SPI interrupt routine
Each time SPI transmits a byte, must have an interrupt, causes the procedure to skip to the SPI interrupt routine. Because SPI main from machine the shift register may regard as is a distributional 16 end around shift register, moreover when while the data carries over from the main engine from machine, the data also high machine carries over the main engine, therefore in the interrupt routine, should first judge in SPDR the data whether is the data which needs to receive (correlative value), then judges in the SPI buffer the data (related code) whether to send, if does not have, then continues to transmit, until sends. The concrete program is as follows:
spi_int:push xl; Preserves register’s value
push xh
in xl, sreg
push xl
lds xl, rcormark; Judges whether is the valid data, “0″ for effective
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in xl, spdr
sts incorbuf, xl; Stores incorbuf the correlative value
spi_2: lds xl, spififoo; Compared with the buffer input, outputs the indicator
lds sprx, spififoi
cp xl. sprx;
breq spiend; Equal, then the data sends, jumps
ldi xh,$9; Different, then takes down a byte to send in spdr
ld sprx, x
out spdr, sprx
cpi xl, $0e0; Adjusts the spififoo indicator
brlo spi_0; Has not surpassed the buffer scope, jumps
ldi xl, $0c2; Surpasses, starts the buffer
The site gives spififoo
spi_0: sts spififoo, xl;
spiend:pop xl
out sreg, xl
pop xh
pop xl
reti
5 concluding remark
This design proposal through the software and hardware debugging, had indicated finally: At-mega103 monolithic integrated circuit compares the 89C5X series monolithic integrated circuit has the very big enhancement in the resources and the function, not only controls is simpler, is nimble, moreover can save many peripheral circuits, therefore has in the cost and the volume superiority, may satisfy the frequency-hopping signal processing module completely the function request.
