Abstract: Introduced in detail the PIC monolithic integrated circuit uses the SPI way and the IC card carries on the data transmission the principle and the circuit design, as well as uses the USART way and PC machine carries on the serial asynchronous communication the principle of work; Introduced that the PIC monolithic integrated circuit listens to the SPI way and the USART way establishment method.
Key word: PIC monolithic integrated circuit IC card reader-writer SPI way USART way
Introduction
This design’s main purpose is introduces the IC card the data storage technology and the IC card data communication, thus use memory card. Because in this design both may carry on the serial synchronous communication with the IC card, and must carry on a line of asynchronous communication with the superior machine, thus needs to choose one kind simultaneously to have these two kind of mailing address monolithic integrated circuit. Because PIC16F877 not only has two mailing addresss which this design needs, moreover also has the running rate quickly, the low power loss, the price low status merit, therefore chooses the PIC16F877 monolithic integrated circuit to take this design the monolithic integrated circuit.
Figure 1 is this design circuit diagram, in the chart power source indicating circuits and so on transfer network and light emitter diode has not drawn. In the chart diode circuit is the monolithic integrated circuit and the IC card correspondence data line protection circuit. When in the data line voltage is a negative voltage, with place connected diode breakover; When in the data line voltage is bigger than 5V, with 5V connected diode breakover, thus in the guarantee data line’s voltage between 0V~ 5V, protects the monolithic integrated circuit and the IC card is not damaged. In chart monolithic integrated circuit’s 15 feet and 23 feet separately with IC card output pin 3 and 4 connected. Because the IC card’s output voltage is the CMOS level, but the monolithic integrated circuit can the correct recognition IC card output signal, need to add on pulls the resistance.
1 SPI working
Serial auxiliary equipment connection SPI (Serial Peripheral Interface) the bussing technique is one kind of synchronized serial interface which Motrola Corporation promotes. The SPI main line is one kind of three synchronous bus, because its hardware ability is very strong, is quite simple with the SPI related software, enables CPU to have more time to handle other business, therefore obtains the widespread application.
The SPI pattern permits 8 bit data synchronization transmission and the receive, supports SPI all four ways. The SPI pattern transmission data needs four holding wires: Serial data output (SDO) line, serial data input (SDI) line, serial clock (SCK) and from choice (SS). And, only uses from the choice line being subordinated the pattern.
1.1 SPI principal-mode -like
As a result of the control clock SCK output, principal-mode -like may start to transmit the data at any time. Principal-mode -like through software agreement control from pattern data output.
In principal-mode in the formula, once the SSPUF register reads, the data will transmit or the receive. When receives the data, SSPSR register according to clock rate shifting, once receives to a byte, the data transmits SSPBUF, simultaneously interrupts the flag bit and the condition flag bit setting.
Clock’s polarity may through the programming change. In principal-mode in the formula, the clock SCK frequency may establish is: fosc/4 (i.e. Tcy), fosc/16 (i.e. 4Tcy), fosc/64 (i.e. 16Tcy) and the timer 2 (Timer2) outputs two frequency divisions and so on four kinds. When the chip clock is 20MHz, the SCK biggest frequency is 5.0MHz.
In this design, the use is SPI principal-mode -like, controls clock SCK by the monolithic integrated circuit the output. When writes the data to the IC card, momentarily may transmit the data; When reads in the IC card the data, must transmit the random data first (this time IC card not to be at reads in condition, will not receive this data), will provide the output data to the IC card the clock, will then receive the data which again the IC card will send out. Its succession as shown in Figure 2. (transmission and meets data which is concerned about is 6FH)
If must transmit the data continuously, then after each time delivers the data the SSPBUF register, must judge whether already to transmit this data, namely judges PIR1 register’s SSPIF position whether is 1. If the SSPIF position is 1, then indicated that the data already end of transmission, might continue the transmission next data. But this time has not been able immediately the transmission next data, because the SSPIF position must in the procedure by the software reset, only then after SSPIF position software reset, can continue the transmission next data.
1.2 SPI from pattern
In SPI from the pattern, the data transmission and the receive is in the lead the outside clock pulse which on the SCK pin inputs, when after last is locked saves, interrupts flag bit SSPIF (PIR1 D3) the position. In the dormancy pattern, still might transmit and receive the data from the pattern, once receives the data, the chip awakens from the dormancy. If uses the SS control from the pattern, when the SS pin receives VDD, SPI pattern replacement; If the color CKE=1 control from the pattern, must open the SS pin control.
In this design, because the IC card is the memory card, cannot provide the clock signal, therefore cannot use from the pattern, can only use principal-mode -like, controls the clock signal by the monolithic integrated circuit.
Monolithic integrated circuit’s SPI way initialization routine is as follows:
MOVLW20H; Delivers the accumulator 20H
MOVWF SSPCON; Delivers the SSPCON register accumulator’s in number
BSF STATUS, RP0; Will decide the RAM area the 1st page
BCF SSPSTAT, SMP; SSPSTAT register’s SMP position 0
BSF SSPSTAT, CKE; SSPSTAT register’s CLK position 1
BCF TRISC,3; Establishes port C 3rd as the output
BCF TRISC,5; Establishes port C 5th as the output
And, the above 1st, 2 lines of procedures dispose the control register, the SPI way disposition is the master control pattern, the clock rate for the monolithic integrated circuit clock rate 1/4, and establishes clock’s high level as the idling condition. The 3rd line of procedure is the form feed instruction, changes to the 1st page the indicator. Because the PIC16F877 monolithic integrated circuit’s data-carrier storage is the paging, but must operate register in the 1st page, must therefore use the form feed instruction the indicator to the 1st page. The 4th, 5 lines of procedures are the configuration state registers, establishes the SPI way as the data output clock’s middle sampling, the clock SCK rise along triggering. The 6th, 7 lines of procedures are establish RC mouth RC3 and RC5 as the output.
2 USART ways
The general synchronized asynchronous receive transmission module (USART) is one of two serial communication connections, USART is called SCI (Serial Communication Interface). USART may establish as the full-duplex asynchronous serial communication system, this way may with auxiliary equipments and so on personal computer PC or serial interface CRT carries on the serial communication: May also establish as the half-duplex asynchronous serial communication system, with serial interface A/D or D/A component connections and so on integrated circuit, serial EEPROM. USART is the two-wire system serial communication connection, it may define the following three working: Full-duplex asynchronous system, half-duplex synchronization master control way, half-duplex synchronization driven way.
For establishes separately RC6 and RC7 the serial communication connection the transmission/clock (TX/CK) the line and the receive/data (TX/DT) the line, must first (TCSTAT RD7) and direction register TRISC D7:D6 sets the SPEN position 1.
The USART functional module includes the condition which two 8 may read/writes/to control the register, they are transmission mode/control register TXSTA and accepting state/control register TCSTA.
USART has 8 baudrate generator BRG (Baud Rato Generator), this BRG supports USART the synchronization and the asynchronous working. Controls an independent 8 timer’s cycle with the SPBRG register. Under the asynchronous system, the transmission mode/control register TXSTA BRGH position (i.e. D2) is also used for to control the baudrate (to neglect under synchronous mode the BRGH position).
Reads in a new starting value when to baudrate register SPBRG, will cause the BRG timer to reposition the reset, from this may guarantee that after BRG does not need to wait till the timer will overflow, may output the new baudrate.
Carries on the initialization to the USART way the procedure to be as follows:
BSF STATUS, RP0; The indicator direction data-carrier storage’s 1st page
MOVLW 0×19
MOVWF SPBRG; The establishment baudrate is 9600
BCF STATUS, RP0; The indicator direction data-carrier storage’s 0th page
CLRF RCSTA; Will receive the control and the condition register reset
BSF RCSTA, SPEN; Serial port permission
CLRF PIR1; Elimination interrupt symbol
BSF STATUS, RP0; The indicator direction data-carrier storage’s 1st page
CLRF TXSTA; Will transmit the control and the condition register reset
BSF TXSTA, BRGH; Establishes for asynchronous, the high speed baudrate
BSF TXSTA, TXEN; Permission transmission
BCF STATUS, RP0; The indicator direction data-carrier storage’s 0th page
BSF RCSTA, CREN; Permission receive
After the initialization completes, then transmits or the receive data. When transmission or receive data, interrupts the flag bit through the inquiry transmission/receive then to judge whether to transmit a data/to receive to a data. The transmission/receive interrupt sign does not need not the useful software to reposition.
In asynchronous serial transmission process, so long as TXREG register for spatial, the interrupt symbolizes TXIF on the setting. Therefore, TXIF was 1 is not the end of transmission symbol, but still might use the TXIF sign to judge. Therefore when TXREG is a free time, sends in after the data, the data will retain in the TXREG register, will emigrate until the preceding data from the transmission shift register, namely the preceding data will transmit.
3 IC cards
The IC card is integrates the electricity tax office outpost (Integrated Circuit Card) the abbreviation, some countries and the address call it the smart card (Smart Card), the chip card (Chip Card). The International Standardization Organization (ISO) stipulated in the ISO7816 standard that the IC card is refers to, in (PVC) or the polyvinyl-chloride sour fat (PVCA) the material is made by the polyvinyl-chloride in plastic card embedded IC chip and so on processor and memory data cards. In recent years, because led half body technology the progress, the integrated degree and the storage capacity had the very big enhancement, and caused CPU and the memory integration on a chip, thus enhanced the data security.
In this design, what the IC card uses is at45DB041B-SC chip, this chip characteristic like:
* sole 2.7V~3.6V power source;
* serial interface structure;
* page programming operation, sole circulation redundant programming (cleaning and programming, 2048 pages (each page of 264 bytes) main memory;
* two 264 byte SRAM data buffer, the permission when is programming the nonvolatile storage again receives the data;
* built-in programming and control timer;
* low power loss, 4mA active read electric current, 2μA CMOS spare electric current;
*15MHz biggest clock rate;
* serial periphery connection way (SPI) - - pattern 0 and 3;
*CMOS TTL compatible input and output;
*5.0V may withstand input, SI, SCK, CS (low level effective), RESET (low level effective).
In this design’s debugging process, once had tested the IC card input power output, finally proved that this kind of IC card the input level and TTL are compatible, but the power output and TTL are incompatible.
4 IC card’s power source provides the electric circuit
In this design, because the IC card’s supply voltage scope is 2.7~ 3.6V, but the PIC monolithic integrated circuit needs the power source is 5V, moreover the constant voltage source provides the voltage is also 5V, therefore, must design a constant voltage module, provides about 3V to the IC card the voltage. Designa circuit as shown in Figure 3.
This electric circuit’s key element is the LM317 chip, it is three end adjustable integration manostat, the output voltage is in the 1.25~37V scope adjustable. When its Vin end’s input voltage changes when the 2~40V scope, the electric circuit can the normal work, out-port Vout and the adjustment carries ADJ the voltage to be equal to voltage reference 1.25V. In this chip’s base electric circuit’s operating current IREF is very small, approximately for 50μA, provides by a constant flow very good constant current, therefore its size power line voltage’s influence, is been unstable. In Figure 3, B spot is the voltage out-port, is the IC card provides the voltage. A spot is the control end, is connected with a monolithic integrated circuit’s port pin, when this pin for low level, triode Q1 does not work, B output voltage approximately is 3.15V; When this pin for high level, the triode Q1 work, B output voltage approximately is 1.25V. Inquires in the IC card plug in the procedure whether to have the IC card, when has the IC card, establishes A spot company’s monolithic integrated circuit pin as the low level, thus is the IC card provides the power source; When does not have the IC card or finished to the IC card’s operation, A spot monolithic integrated circuit pin continually establishes as the high level, thus did not provide the power source to the IC card.
The IC card’s on electricity and under the electricity procedure is as follows.
In IC card under electronic program IC card electronic program
POWERON POWEROOF
BSF STATUS, RP0 BSFSTATUS, RP0
BCF TRISE,0 BCF TRISE,0
BCF RTISE,1 BCF TRISE,1
BCF STATUS, RP0 BCF STATUS, RP0
BCF PORTE,0 BSF PORTE,0
BCF PORTE,1 BSF PORTE,1
CALL DLYTIM CALL DLYTIM
RETURN RETURN
In this design, the monolithic integrated circuit and IC card correspondence’s master routine flow chart as shown in Figure 4.
5 and PC machine correspondence
In this design, has the PIC monolithic integrated circuit and the PC machine serial communication function. Because this design uses monolithic integrated circuit PIC16F877 has the USART way, this way may establishes C RC5 and RC7 the asynchronous serial communication pattern, thus in this design, is quite simple with the PC machine connection module electric circuit. Establish monolithic integrated circuit C RC6 and RC7 as the asynchronous serial communication pattern, carries on the level switch after the MAX232A chip, the TTL level switch is the RS232 level, is again connected with the DB9 connection, then realizes the correspondence. In the PC machine end, may use VC and so on to program the tool to control according to the communication protocol compilation software to the IC card read-write operation.
6 conclusions
After the debugging, this design can in is separated from the online simulator’s situation, after on the electricity, the independent operating procedure, and can under the PC machine software’s control, realize to the IC card in the optional position read-write, the read-write start address, the read-write data’s integer as well as the data content may in the PC machine end input or the choice.
This design has tested in the practical application, has the use value. Because in this design uses the PIC monolithic integrated circuit’s program memory is big (8KB), thus may compile the big procedure, which kind of chip IC card realizes unites this card and by PC machine the control read-write. Moreover, because this design uses monolithic integrated circuit’s program memory is the Flash memory, thus may realize procedure downloading and the promotion conveniently.
