In digital image processing, the aerospace and so on high speed signal processing application situation, needs to have the high speed large capacity storage space force support, satisfies the system to the mass data turnover request, through uses large capacity synchronized dynamic RAM (SDRAM) to expand the embedded DSP system storage space the method, selects ISSI Corporation’s IS42S16400 the high speed SDRAM chip, detailed elaboration in based on TMS320C6201 (i.e. C6201) in digital signal processing system this design method concrete realization.
1 IS42S16400 chip synopsis
IS42S16400 is ISSI Corporation promotes one kind of monolithic storage capacity which reaches as high as 64Mb (i.e. 8MB) 16 word width high speed SDRAM chip. The SDRAM main feature is:①The synchronized visit, the read-write operation needs the clock;②The dynamic storage, the chip needs fixed time refurbishing. IS42S16400 uses the CMOS craft, its synchronized connection and the complete assembly line’s internal structure enables it to have the enormous data transfer rate, may work in reaches as high as under the 133MHz clock rate, refurbishing frequency each 64ms is 4096 times. This SDRAM chip interior has 4 storage media (bank), passes goes through another firm as a middleman, the row address time sharing multiplying system address bus, the different page’s concrete memory cell carries on the read-write addressing visit to the different storage medium. In carries on reads between the operation, must activate the storage medium which in advance in SDRAM corresponds, and chooses memory’s some line, then sends in the data which the row address read needs. From loses leaves ranks to return to between the corresponding data the address to SDRAM to have an access delay. If visits the new page, then needs to close all storage media first, otherwise has opened page continuously effective. Before writing the operation, because already in advance activated the related good address, therefore may while loses leaves ranks the address output data, has not retarded. IS42S16400 provides from the refurbishing pattern establishment, may cause the chip movement under the low power loss condition, thus reduces embedded system’s power dissipation greatly.
2 C6201 and SDRAM exterior memory interfaces
When DSP chip visit piece external memory must pass exterior memory interface EMIF (External Memory Interface). C6000 series DSPs EMIF has the very strong connection ability, not only has the very high data turnover rate (to reach 1200MB/s high), moreover may with at present the nearly all type memory direct connection. In the C6201 system, has provided 4 each other independent external memory connection (CEx). Besides the CE1 space only supports the asynchronous connection, all exterior CEx space supports to the SDRAM direct connection. Table 1 summarized C620X DSPs EMIF the compatible SDRAM disposition. Table 2 have given the SDRAM control command which C6000 series DSPs EMIF supports.
2.1 SDRAM refurbishing
In order to enhance the storage capacity, SDRAM uses the silicon chip electric capacity canned data. With the lapse of time, must recharge to the electric capacity can maintain in electric capacity’s data message, this is so-called “refurbishing”, its existence also causes SDRAM the application changes slightly obviously complex, has brought certain application difficulty.
C6000 series DSPs has the special SDRAM control register (SDTCL) and the SDRAM sequential control register (SDTIM), uses for to carry on SDRAM each kind of sequential control, reduced designers’ development difficulty greatly, SDCTL in register’s RFEN position has controlled whether to complete by EMIF to SDRAM refurbishing. If RFEN=1, EMIF will control to all SDRAM space issues the refurbishing order (REFR); But SDTIM in register’s PERIOD position section controls the concrete refurbishing cycle.
Before the REFR order, an automatic insertion DCAB order, will guarantee in the refurbishing process all SDRAM not to be at the state of activation. After DCAB order, EMIF starts according to the SDTIM register in the PERD field establishment value to carry on fixed time refurbishing. Around refurbishing, the page information will become invalid.
Control module interior has 2 counters regarding C620X, EMIF the SDRAM, uses for to monitor the submission the refurbishing application number of times. Submits an application every time, the counter adds 1; After each time refurbishing cycle, the counter reduces 1. When replacement, the counter sets is 11b automatically, guaranteed before deposit visit carries on certain refurbishing first. The counter sets is 11b automatically, represents the urgent refurbishing condition, this time the page information register changes invalid, forces the controller closure current SDRAM page. Then, EMIF SDRAM controller after the DCAB order carries out 3 REFR orders, causes the counter the value to reduce is 0, continues completes in addition the accessing operation again.
2.2 SDRAM initialization
After some CE space disposition is the SDRAM space, must first carry on the initialization. The user does not need to control initialization each step, only needs to EMIF SDCTL register’s INIT position to write 1, applies to make the initialization to SDRAM. Then, EMIF automatically will complete each step which will need the operation. The initialization operation cannot in carry on the SDRAM access procedure to carry on. Entire initialization process including the following several steps:
①Issues the DCAB order to all SDRAM space;
②Carries out 3 REFR orders;
③Issues the MRS order to all SDRAM space.
2.3 page boundary control
SDRAM belongs to the paging memory, the EMIF SDRAM controller can monitor visits the SDRAM fashionable address the situation, avoids when the visit has the line to cross the border. In order to complete this task, EMIF has four page registers in the interior, the automatic preservation current opens the good address, then carries on the comparison with the following deposit visit’s address. What needs to explain, the current accessing operation will end will not cause the line which in SDRAM already activated to close immediately, the EMIF control principle was the maintenance current opens the condition, only if must close. Does this between the advantage is may reduce the closure/to open the order switching time, causes the connection in the memory visit controlled process the full use address message.
Regarding C620X, each CE space contains 1 page register (only to dispose is the SDRAM space effective), therefore C620X each CE space 1 time can only activate 1 page. Carries on the comparison the address figure to be decided in the SDCTL register the SDWID position value. If SDWID=0, this CE space constitutes page’s size is 512, compared with the logical address is the position 23~11; If SDWID=1, this CE spatial SDRAM constitutes page’s size is 256, compared with the logical address is the position 23~10. Once the discovery deposit visit had the page to cross the border, EMIF will carry out the DCAB operation automatically, then started the new line of visit again.
2.4 visit address shifting
Because SDRAM good logical address with the row logical address multiplying same EMIF pin, therefore the EMIF connection needs to carry on corresponding shifting processing to the good address with a row address. Address shifting processing position controls by SDCRL in register’s SDWID.
Moreover, regarding SDRAM, because the entry address is also the control signal, therefore needs to explain the following several points:
①The RAS validity duration’s high address signal controller lock will be saved by EMIF the internal SDRAM, guaranteed will carry out READ and when the WRT order will select correct bank;
②READ/WRT operation period, EMIF will maintain the pre-charge signal for low (C620X is SDA10), after will prevent READ/WRT will order the execution, to have the auto-pre-charge operation.
2.5 connection succession design
Controls regarding C620X, EMIF and the SDRAM connection succession by the SDCTL register. EMIF has provided 5 succession parameters, 3 establish in the SDCTL register, other 2 are the fixtures, like Table 3 arrange in order. When analysis connection succession coordinate situation, needs to calculate “the wealthy time” the tmargin size, this is after having considered the SDRAM chip’s component handbook provides worst situation, obtains in a succession allowance, as for the tmargin value’s size, is the question which the system design level needs to consider, specific request along with different system, but different, moreover is closely related with the board actual wiring situation as well as the load situation.
in 3 system designs IS42S16400 chip application
3.1 C6201 and the IS42S16400 connections realize
Because IS42S16400 belongs to 16 word width 64Mb the SDRAM chip, but C6201 EMIF only provides 32 word widths the synchronized external storage connections, to cause overall system’s storage space maintains continuously, uses 2 piece of SDRAM and the DSP chip composition actual size is the 16MB exterior memory system, as shown in Figure 1. Figure 1 IS42S16400 chip various pins meaning is as follows: CS, selects patches or strips of land as worth saving for seed; CLK, system synchronized clock; RAS, good address selection; CAS, arranges in order the address selection; WE, reads/writes enables; CKE, the clock enables, DQMU, DQML, the height byte enables; A[13:12], Bank address selection line; A[11:0] line, row address first; DQ[15:0], bidirectional data port.
May see by Figure 1, although C6201 provides 32 bit address addressing ability, but after EMIF direct output address signal only then EA[21:2]. In ordinary circumstances, EA2 signal correspondence logical address A2, but this does not mean when DSP chip visit external memory can only carry on word (32) deposit, actual internal 32 bit address lowest 2~3 after decoding outputs by BEx, is can the control byte visit. Top digit logical address after decoding outputs CE[3:0].
In the actual system realizes, the C6201 CLKOUT1 clock rate is 200MHz, therefore the SDRAM practical work frequency is 100MHz, (SDCLK=CLKOUT2=CLKOUT1 frequency/2), namely tcyc=10ns. SDRAM is disposed in the CE2 space (outset logical address is 0×02000000).
3.2 C6201 EMIF SDRAM register establishment
Table 4 listed has disposed the EMIF register name which and the corresponding position or the position section SDRAM needed to establish.
EMIF in the overall situation control register’s SDCEN position, (position 6) establishes is 1, uses for to enable SDRAM synchronized clock SDCLK the output. EMIFEC2 in the space control register’s MTYPE position section (position 6~4) establishes is 011b, uses for to dispose CE2 is 32 bit wide SDRAM spaces. May look up tRC=70ns, tRP=18ns, tRCD=18ns by the IS42S16400 data book, therefore EMIF SDRAM in the control register’s TRC position section (position 15~12) should establish is the 0110b, TRP position section (position 19~16) should establish is the 0001b, TRCD position section (position 23~20) should establish is 0001b. The INIT position (position 24) sets 1, uses for to force to SDRAM to carry in the electricity initialization. The RFEN position (position 25) sets 1, uses for to enable EMIF to SDRAM refurbishing. The SDWID position (position 26) sets 1, uses for to EMIF to indicate uses the SDRAM chip’s word width is 16, as a result of IS42S16400 refurbishing frequency for each 64ms4096 time, therefore according to formula PERIOD=trefresh/tcyc, EMIF SDRAM in the sequential control register’s PERIOD position section (position 11~0) by the establishment is 0×61A.
In 3.3 CCS development environment SDRAM disposition procedure source code
TI Corporation’s integrated development environment CCS (Code Composer Studio), IS42S16400SDRAM the chip disposition procedure C code is as follows:
#include<emif.h>…/* other user program *//* reads out EMIF to control register’s default setting */
unsigned int g_ctrl=GET_REG (EMIF_GCTRL);
unsigned int ce0_ctrl=GET_REG (EMIF_CE0_CTRL);
unsigned int ce1_ctrl=GET_REG (EMIF_CE1_CTRL);
unsigned int ce2_ctrl=GET_REG (EMIF_CE2_CTRL);
unsigned int ce3_ctrl=GET_REG (EMIF_CE3_CTRL);
unsigned int sdram_ctrl=GET_REG (EMIF_SDRAM_CTRL);
unsigned int sdram_ref=GET_REG (EMIF_SDRAM_REF);
the/*EMIF overall situation control register - enables SDCLK*/
SET_BIT (&g_ctrl, SDCEN);
/* establishes CE2 is SDRAM spatial */
LOAD_FIELD (&ce2_ctrl, MTYPE_23SDRAM, MTYPE, MTYPE_SZ);
/* establishes SDRAM control register */
LOAD_FIELD (&sdram_ctrl,6, TRC, TRC_SZ);
LOAD_FIELD (&sdram_ctrl,1, TRP, TRP_SZ);
LOAD_FIELD (&sdram_ctrl,1, TRCD, TRCD_SZ);
SET_BIT (&sdrrm_ctrl, SDWID);
SET_BIT (&sdrrm_ctrl, INIT);
SET_BIT (&sdrrm_ctrl, RFEN);
/* establishes SDRAM refurbishing cycle */
LOAD_FIELD (&sdram_ref,0×61A, PERIOD, PERIOD_SZ);
/* compounds EMIF again control register */
emif_inif (g_ctrl, ce0_ctrl, cel_ctrl, ce2_ctrl, ce3_ctrl, sdram_ctrl, sdram_ref);
…/* other user program */
Conclusion
Above introduced TMS320C6201 DSP chip and SDRAM (IS42S16400) the concrete hardware interface realizes. Because SDRAM has large capacity, the high velocity and the low price superiority, will use SDRAM to construct the embedded application mass memory system to become one effective method. At present this system has debugged finishes. Uses SDRAM as the DSP system external connection high speed, the large capacity main storage to have the very obvious superiority, has demonstrated SDRAM fully in embedded system’s good application prospect.
