Abstract: Introduces ADI Corporation TigerSHARC series DSp the vectoring procedure load principle and the application. Gives TigerSHARC the series DSP program load several kind of patterns, mainly take TS20lS DSP as the example explained the list DSP system program loads process and method. This design has the versatility in TigerSHARC in series DSP. May apply the design which conveniently loads in other DSP vectoring procedure.
Key word: DSP; TigerSHARC; Vectoring procedure; Load; Connection; TS201S
Along with the DSP technology’s development, the DSP function is getting stronger and stronger, the type are also getting more and more. As a result of the DSP internal structure’s characteristic, the DSP algorithmic routine saves generally in the exterior nonvolatile storage, after system electricity, must load the algorithmic routine from the exterior memory to DSP, carries on corresponding data algorithm processing again.
TS20lS was ADI in Corporation TigerSHARC series integrated fixed-point and floating-point computation function high speed DSP. The processor work in 600MHz, the monocycle can carry out 4 instructions, each second can carry on 340,000,000 times while the accumulation and 280,000,000 floating point operations, is faces the correspondence and video frequency domain high-end DSP. TS201S including 24Mbit internal DRAM; 1 14 channel’s DMA controller: 4 chain street intersections may use in with other DSP carrying on the seamless joint. Composes more than a DSP processor system, each chain street intersection’s data rate may reach 1GB/s; Integrates the SDRAM controller to support 256M x 32bit most greatly the memory capacity, the convenience and the exterior SDRAM connection. TS20lS is suitable to the great data quantity data processing timeliness to request the high application domain.
TigerSHARC the series DSP connection is rich, its vectoring procedure’s load method is also flexible, may need to select nimbly according to the reality system design.
1 TigerSHARC series DSP guidance pattern
The DSP guidance is in the DSP system reset situation from the DSP exterior memory loading algorithmic routine code process. TS201S supports two kind of guidance patterns: Main guidance (master boot) pattern and from guidance (slave boot) pattern.
Under the main guidance pattern, TS201S takes the initiative side, with the exterior output address, reads, control signals and so on guidance mode selection (BMS), loads the code from EPROM or Flash. From guides under the pattern, TS201S takes the passive side, not to the exterior output control signal, the exterior main engine or other equipment to the TS201S main engine, the link transmits orally the code which delivers must load, TS201S only starts certain DMA channel, and carries out the load nucleus which first DMA receives.
Moreover, TS201S may also choose one kind “the non-guidance” the pattern, either using TS20lS (simulator) the EZ-ICE loading sequence, this way may directly in program load TS201S internal RAM or exterior RAM, DSP directly from RAM the operating procedure, commonly used in the DSP debugging process.
Through to the TS20lS BMS pin’s establishment, may establish the DSP guidance process the main guidance pattern or from the guidance pattern. In DSP replacement period, if BMS low level, then chooses the main guidance pattern, DSP from exterior EPROM or Flash loading sequence; If the BMS pin is the high level, enters from the guidance pattern, DSP is the idling condition, waits for the main engine or the chain street intersection loading sequence. 2 kind of guidance patterns have the same load process. The concrete step is as follows:
(1)TS201S automatic start DMA. (32) transmits automatically 256 characters to internal memory’s address 0×00-0xFF.
(2)TS201S carries out the above 256 character instruction (load nucleus), the load nucleus starts other DMA, loads the following instruction and the data to the interior and/or in the exterior memory.
(3) load nucleus self-cover, carries out the DSP algorithmic routine.
2 list TS201S program load connection design
When TigerSHARC series TS20lS takes the single DSP use, mainly has 3 guidance ways.
2.1 exterior EPROM guidances
The exterior EPROM guidance guides the pattern primarily, is the most commonly used guidance pattern. Under this pattern, the BMS pin and the RD pin enable the pin as EPROM selecting patches or strips of land as worth saving for seed with the output. The EPROM 8 bit data line meets TS201S DATA0-DATA7. TS20lS supports 16M most greatly the EPROM address space, its low address pin and the EPROM address pin is connected. Shares main line’s system regarding the multi-processor, available EPROM to all TS201S load. Shown in Figure 1 is ST Corporation’s Flash (DSM2150) and the TS201S program load connection design example.
After the replacement, the DMA channel 0 are disposed automatically, DMA corresponding 2 TCB register (Transfer Control Block) by initialization, then from 8 exterior EPROM address 0 starts, transmits a 256 character’s load nucleus to internal memory address 0×00-0xFFo. DMA channel 0 interrupt vector initialization for internal memory address 0×00. When the DMA channel 0 transmissions complete, has the interrupt, TS20lS starts from the 0×00 execution load nucleus. Then, load nucleus through a string individual character DMA transmission the following application code and data load. Finally, the load nucleus starts 256 characters DMA, causes its oneself by the user application procedure code cover. When this DMA process completes, the DMA channel 0 interrupt vector population address for the internal memory address 0, user’s application code 0 starts from the address to carry out. The TS20lS exterior connection is 32 bit data widths, therefore TS201S in through DMA channel loading sequence time, uses automatically 8 to 32 special-purpose pack ways, the low position before, completes reads from EPR()M DMA. Only the DMA channel 0 support this special-purpose pack way, therefore the vectoring procedure must use DMA0.
Moreover, in the algorithm application program run stage, the essence cannot use the instruction to enable BMS the way to carry on directly visit to EPROM, but may through the DMA channel way visit. This is because EPROM is the byte addressing space, it does not belong to the TS201S memory space. Exterior EPROM occupies the biggest storage space is the 16M byte, because E-PROM is the slow peripheral device, reads visit to EPROM each, TS201S must wait for 16 cycles. TS201S reads succession as shown in Figure to exterior E-PROM 2.
2.2 main engine guidances
When uses the main engine (HOST) guidance pattern, 32 or 64 main engines complete through the exterior data and the address bus to the TS201S guidance. TS201S available any Auto the DMA channel carries on the code transmission under the main engine guidance way. Other processes guide same as exterior E-PROM. The main engine monitors Auto DMA through DSM condition register (DSSTAT) the condition. The TS201S external bus width is established in a default’s situation 32, therefore the main engine must use the assembly line agreement and TS201S carries on the correspondence.
2.3 chain street intersection guidance
TS201S has 4 chain street intersections (Link Port), each chain street intersection may use in the vectoring procedure the load. Its load process and the main engine guidance pattern are similar.
more than 3 TS201S program load connection designs
In the actual system design, in processes the high data stream and under the great data quantity condition uses many DSP cascades frequently. Carries on the program load to many DSP, with EPROM, HOST, LINK PORI, the load pattern may realize.
Under the EPROM guidance pattern, pin receives each DSP Li the BMS the same place, connects EPROM to select patches or strips of land as worth saving for seed on the signal, the exterior address, the data also distinguish the company to arrive at EPROM the data, on the address bus, each DSP visits EPROM in turn according to the main line priority. EPROM guides multi-DSP another method is after the main DSP(ID2-0=000) load completes, 0 reads in the load code through the multi-DSF memory space to other DSP AutoDMA channel, completes other DSP the program load. This method only then advocates the DSP RD pin and EPROM selects patches or strips of land as worth saving for seed connected, other. The DSP RD signal on pulls on the resistor through exterior to pull.
Under the HOST load pattern, the main engine according to the running water agreement, guides other DSP with HBR and the HBG signal.
In the multi-DSP system LINK the PORT load way is the most nimble one program load way, may the front two kind of load pattern union use, when first DSP uses EPROM. After or HOST loads successfully, may load other DSP in turn according to the chrysanthemum catenuliform type by first.
4 vectoring procedure design
Below explains the TS20lS vectoring procedure take the EPROM guidance pattern as the example the design method. ADI Corporation’s visual the DSP tool provides the program load application procedure (elfloader.exe) may and loads the DSP algorithmic routine the nuclear procedure merge production: EPROM load output file (*.ldr). How does this load output file use for to define in the load process the TS201S interior and the exterior memory by the initialization, its form as shown in Figure 3. And the data marking block is selected form definition as shown in Figure which signs 4.
In the DSF program load process’s quite complex process is loads the nucleus the self-cover. When the data marking block is selected the high 3 data which signs is when O (sees chart 4, TYPE=0), the load nucleus execution “the conclusion loaded” the process, covered the load nucleus with the DSt algorithm code 256 character procedures. This is loads the process last DMA, awakens DSP from the IDLE condition, completes the load nucleus the self-cover, but, the simple self-cover can make the DSP algorithmic routine to start from the DMA0 interrupt level to carry out, this does not hope. In order to solve this problem, realizes through the following algorithm.
the (1)DSP algorithm code’s first 4 character is saved in xRll:8.
(2) below the code will read in Ox 1 Ox00000003 RETI=0; ; NOP; ; RTI(NP); ; QD31 =0] =xRl 1:8; ;
the (3)DMA interrupt vector establishes as the address 0.
(4) establishment address buffer invalid (BTBINV) eliminates in the buffer any branch address.
(5) puts 256 user codes 0×00000004-0×000000FF.
(6) pair of TCB programming, starts DMlA, the processor enters the IDLE condition.
after (7)DMA completes, responds the DMA interrupt, the program timer jumps to address 0×00000000, starts to carry out the following code: RTI (NPl; ; Q [j3 l =0] =xRll:8; ; .
These instructions cause the interrupt to degrade, the user DSP algorithmic routine puts 0×00000000-Ox00000003, the instruction counter refers to the needlework to the address 0×00000000(), user’s algorithmic routine starts from 0×00000000 to carry out, this time the algorithmic routine is not in the interrupt level. Here NP option is must, cause: RTI instruction not cushion: In BTB.
If in system’s exterior memory must by the special initialization (for example SDRAM), then this memory must dispose and the initialization by the essence. The load nucleus must revise and translate, the final load nuclear code cannot surpass 256 characters, is by: The DSP characteristic decides.
5 concluding remark
ADI Corporation’s high performance Tiger SHARK series TS201S DSF in has requested the high situation to the real-time processing to obtain the widespread application, like correspondence base depot, airborne radar approach early warning, array signal processing and so on. In the article elaborated its program load connection emphatically, introduced DSF loads several kind of commonly used patterns, and have given one kind of practical connection plan. In the software aspect, has given the explanation to the DSP load process’s difficulty. In the article mentioned several DSP program load method is also suitable for other type DSP, the reader may utilize nimbly it in the actual DSP system design.
