Abstract: The C8051F series monolithic integrated circuit is the high speed monolithic integrated circuit which Cygnal Corporation produces, it is compatible with the 80C51 series monolithic integrated circuit set of instructions, but increased many resources compared to the latter, thus has provided enormous convenient for embedded system’s development. In the article introduced this both when structure difference as well as programming should pay attention the question, and has given they complete initialization routine.
Key word: Special function register SDR; First power overlapping switch decoder; Overlapping stop-go control register
1 introduction
In the recent 30 years, the world each main electron primary device production manufacturer promotes oneself unique monolithic integrated circuit product in abundance. But in all flowers blooms together in the monolithic integrated circuit family, the 80C5l series has been playing the important role. This monolithic integrated circuit in domains and so on teaching, scientific research already became the basic monolithic integrated circuit and becomes the monolithic integrated circuit application the first choice, this product is good by its readability, expansion ability strong is famous, thus becomes is engaged in the type which generally the monolithic integrated circuit exploiter is most familiar, most has represents. But people often after the familiar 80C51 monolithic integrated circuit chooses other series monolithic integrated circuit develop products, this is because 80C51 has the operating speed to be slow, power loss big, internal resources few and so on insufficiencies, therefore has limited its use scope. Cygnal Corporation promotes the C805lF series monolithic integrated circuit both has made up the 80C51 series insufficiency, and the MCS-5l set of instructions is compatible. The C805lFxxx series monolithic integrated circuit is the composite signal system-on-a-chip which integrates completely, has with 8051 set of instructions completely compatible CIP-51 essence. It integrated in monolithic constituted nearly all simulations which and the digital peripheral device and other functional unit a monolithic integrated circuit data acquisition or the control system needed. These peripheral devices or the functional unit includes: ADC, increases the amplifier, DAC, the voltage comparator, the voltage datum, the temperature sensor, SMBus/I2C, UART, SPI, the timer, the programmable counter/timer array programmable (PCA), the internal neterodyne, the watch-dog timer and the power monitor and so on. These peripheral device part’s high integration rate to design the small volume, the low power loss, redundant reliable, the high performance monolithic integrated circuit application system to provide very big convenient, simultaneously might also cause integrated system’s cost to reduce greatly.
The familiar MCS-51 series monolithic integrated circuit’s engineers and technicians may grasp C8051Fxxx very easily the applied technology and carry on the software to transplant. But cannot apply directly 8051 procedures in the C8051F monolithic integrated circuit, because of these two kind of series monolithic integrated circuit interior resources existence big difference, therefore, imitates, the transplant is completely invalid, must undergo “the improvement” (is mainly initialization control word rewriting) can move correctly. This article the resources most is rich take the C8051Fxxx series monolithic integrated circuit, the function most to be many, the operating speed is quickest (achieves 100MIPS) the C8051F12X series as an example, introduced it with when 80C51 main difference as well as development should pay attention the question, has simultaneously given its completely, and after movement confirmation source program.
Figure 1
2 structure differences
The C8051F12X monolithic integrated circuit has four points with 8051 monolithic integrated circuit’s in structure biggest differences: Outside the pin uses the overlapping switch disposition; The system clock source is diverse, and controls nimbly; Internal special function register SFR type quantity increases; Has based on the JTAG connection in the system debugging function. Below mainly introduces the first three partial contents.
2.1 programmable digital I/O and overlapping switch
Programmable digital I/O and the overlapping switch are big number switch networks, it permits the interior number system resource distribution for the port I/O pin. With has the standard multiplying digit I/O micro controller to be different, this kind of structure support all function combination. May through the establishment overlapping stop-go control register (XBR2, XBR1 and XBR0) the internal counter/timer, the serial main line, the hardware interrupt, the ADC transformation enable input, the comparator will output as well as the micro controller interior other digital signal disposition to appear in the port I/O pin, this enables the user to be possible to act according to own specificly and needs the digital resources using choice general port I/O the combination. But is different basically with 8051 monolithic integrated circuit’s pins is the fixed assignment. The C8051F series through the priority overlapping switch decoder planned target switching network, the priority overlapping switch decoder’s value by the overlapping stop-go control register (XBR2, XBR1 and XBR0) disposes, as shown in Figure 1. The priority overlapping switch decoder starts according to the priority order from P0.0, may assign P3.7, it the port pin’s order of priority which assigns for the digital peripheral device is according to the system default order, namely: Serial communication UART0 has the highest priority, TX0 and RX0 is assigned separately has to P0.0 and P0.1 serial communication SPI a high priority, the detailed port pin’s first assignment sequence chart please refer to the pertinent data. If does not choose some resources, then in the priority sequence table next function will fill this position. Shown in Figure 2 is three overlapping stop-go control register (XBR2, XBR1 and XBR0) everybody’s meaning, their replacement value is 00000000.
When in overlapping switch disposition register XBR2, XBR1 and XBR0 the peripheral device corresponding position is established logic 1, overlapping switch port pin assignment for peripheral device; If a digital peripheral device’s permission position has not been established logic 1, then its port cannot through the pin visit. The overlapping switch assignment port which establishes has not been possible to treat as the standard continual I/O mouth use. After system reset, default register XBR2, XBR1 and the XBR0 value is zero, namely all I/O pin is forced the input port (to take to bring with pulls), and not with internal resources connection. Thus, does not have the output system to be obviously insignificant, therefore, should set at XBR2 6th in any event is 1, causes the overlapping switch permission in order to draw out the output signal.
2.2 system clock sources
The C8051F12X system clock may be from the internal oscillating circuit, the exterior oscillating circuit (including crystal oscillator, the RC vibration, ceramics acceptor) and the phase-locked loop PLL electric circuit, the phase-locked loop PLL electric circuit’s input source may choose from the internal oscillating circuit, may also choose the exterior oscillating circuit, may raise the clock rate through the PLL frequency multiplication function. In C8051F12X system’s oscillating circuit as shown in Figure 3. Must produce the system clock which needs, usually must establish 8 registers: OSCXIN, OSCICN, OSCICL, CLKSEL, PLLOCN, PLLOFLT, PLL0DIV, PLL0MUL, latter 4 are the related PLL registers.
2.3 special function register SFR structure
Is different what with MCS-51 SFR, C8051F12X SFR many pages which by shown in Figure 4 composes, altogether has 5 pages, the page number is 0, 1, 2, 3, 15. Each SFR distributes in the different page, looks like XBR0, XBR1, XBR2, OSCXIN, OSCICN, LLOCN, PLLOFLT and so on to locate in 15 pages, timer related register TCON, TMOD, TH, TL and so on locate in 0 pages. Before read-write each SFR, must cut the corresponding page first, may use “MOV the SFRPAGE,# page number” the instruction to carry on the cut. Which pages each do SFR, please examine the related material.
3 using example
In this example must use to draw out the foot to have outside serial asynchronous communication UART and interrupts INT0. According to the system default’s order of priority, the P0 mouth is drawn out by the internal resources takes, P0.0 is UART the correspondence RX end, P0.1 is UART the correspondence TX end, P0.3 is outside interrupts the INT0 input pin, other ports for the general I/O mouth. The P1 mouth to have on pulls the resistance the input port, the P2 mouth for the general push-pull’s outlet, the P3 mouth is also the general push-pull outlet. Specifically as follows:
$include (c8051f120.inc)
ORG 00H
JMP RESET; Procedure entrance
ORG 03H
JMP EX_INT; Outside interrupts the INT0 entrance
ORG 0BH
JMP TIME_0; Timer 0 interrupt entrances
ORG 100H
RESET 煟 stops hopes Zheng WDTCN,#0DEH 牻 to stop the watch-dog
MOV WDTCN,#0ADH
MOV SFRPAGE, #0FH; Takes the special function register’s 15 pages
MOV OSCXCN,#01100111B; External use clock source choice crystal, frequency range below 30MHz
ORL PLL0CN,#00000111B; Takes PLL with the exterior crystal oscillator the source
MOV PLL0DIV,#00000001B; PLL input after coefficient 1 (replacement default)
MOV PLL0MUL,#00000010B; The PLL frequency multiplication coefficient is 2 (the 25MHz crystal oscillator)
MOV PLL0FLT,#00010001B; After PLL filter parameter (replacement, default is 00110001B)
MOV R4,#0; Detention a while, causes the crystal oscillator to be stable
NNOP1:MOV R5,#0
DJNZ R5,$
DJNZ R4, NNOP1
MOV CLKSEL,#00000010B; The system clock source passes through the phase-locked loop PLL doubled frequency again with the crystal oscillator, produces the 50MHz clock
ANL the OSCICN,#01111111B 牐 splendor city qiao liao respects spatially forbids the internal vibration toweringly
MOV XBR2; #01000000B; Enables the overlapping decoding switch (this instruction to be very important)
MOV P2MDOUT,#11111111B; The P2 mouth sets at the output mode
MOV P3MDOUT,#11111111B; The P0 mouth sets at the output mode (replacement default is 0 opens leaks)
MOV XBR1,#0000100B; Outside the permission interrupts the 0th company to arrive at the port
MOV SFRPAGE, #0H; Takes the special function register’s 0 pages (, because related timer, interrupt SFR in 0 pages)
SETB EX0; Outside the permission interrupts 0
SETB IT0; INT0 drops along the interrupt
MOV TMOD,#21h; Establishes the timer 0 for the way 1, timer 1 for way 2
MOV CKCON,#08h; Chooses the timer 0 clocks is the system clock, the timer 1 clock divides for the system clock 12
MOV TH1,#242; (50/12) the MHz clock has 9600 baudrate counting starting values is 242
SETB TR0; Connection fixed time 0
SETB TR1; Connection fixed time 1
CLR ET1; Forbids the timer 1 interrupt
MOV SCON,#50H; Serial port work in way 1, permission receive, single plane work
SETB ET0; Permits the T0 interrupt
SETB PT0; The T0 interrupt priority is high
SETB EA; Opens the interrupt
MOV SP,#30H; Stack bottom in the 30H unit
MAIN: . ; The above is the procedure initialization
. ; Master routine
.
JMP MAIN
牐 ***** timer interruption subroutine *******
TIME_0:PUSH ACC
MOV TH0,#0H
MOV TL0,#0H
CPL P2.2; In P2 mouth D2 foot output square-wave
POP ACC
RETI
牐 outside ****** interrupts subroutine *******
EX the INT 煟 school winks cherry ACC
MOV A, P1; Takes a byte from the P1 mouth
CPL A
MOV P3, A; Sends out a byte
POP ACC
RET
