Abstract: Introduced realizes DSP using CPLD chip TMS320C6711b and PCI between bridge chip PLX9054 the high speed data transmission system design method, and has given the corresponding system design schematic diagram, simultaneously has carried on the analysis to this system’s performance.
Key word: PCI main line; TMS320C6711b; HPI (host port interface); Local bus; PLX9054
CPLD is one kind of complex user programmable logic component. It operates nimbly, the development is rapid, the investment risk is low, may program many times scratches writes programmable with in the system (In System programmability) and so on characteristics becomes one kind to be possible to optimize the hardware circuit design, and competitive power product. In recent years, along with the micro electron integration craft’s unceasing development, each kind of series’s CPLD might and so on the complete scope duty design provide the complete set for the simple PAL integrated design advanced real-time hardware field upgrade the solution. How will this article give uses Xilinx Corporation’s CPLD component XC9500LV to realize the PLX9054 local bus (local bus) and between the DSP HPI mouth real-time communication method. Uses this kind of design to be possible completes between the main engine and the DSP high speed data transmission by the individual character or the DMA way, the transmission speed may achieve 16Mb/s. This method may widely apply in real-time situations and so on graph, image and animation processing.
Figure 1
1 design demand
1.1 local bus connection request
PLX9054 is the PCI connection special-purpose host from the component, including correspondence, network, floppy disk control, multimedia and so on high performance interface function. PLX9054 may realizes by many kinds of ways from pci the bus end to local the bus end (local bus) the data shift, like direct transmission, DMA control transmission and so on. May realize through pci bus and between local bus by six programmable FIFO different connections arises suddenly the concurrent transmission, simultaneously may also carries on the establishment through serial EEPROM or the PCI master control equipment to the PLX9054 internal disposition register, its simplified diagram as shown in Figure 1. In the chart, through disposes EEPROM to be possible to establish PLX9054 to flatter J as the PCI main line from the equipment 煿 ぷ biao tomb to gather together ㄊ according to, the address bus non-multiplying), under this pattern’s local the bus data width is 16bit, simultaneously, through enables external instrumentation ready signal READY also to be possible to forbid the infinite eruption operation (to shield BTERM bit).
Local the bus end reads, writes the succession basically same, shown in Figure 2 is its individual character read-write operation succession. Take the write cycle as the example, first, PLX9054 through sets at the LHOLD signal to apply for local bus effectively the master control power, after receiving local bus the arbitration response signal LHOLDA, PLX9054 will become local bus master control, along with the postpositioned ADS signal for low, causes address bus signal LA[31:2], the byte to enable signal LBE[3:0] and read-write selection signal LW/R enters the effective condition, after a LCLK cycle, 9054 stop actuating ADS, by now, on the address bus LA[31:2] address signal will maintain effective and maintains a LCLK cycle effectively until the data line in data. On the data line LD[15:0] data signal by the READY actuation, READY expressed that local the bus equipment already prepared, may transmit or the receive data. The BLAST signal provides by PLX9054, the BLAST signal to express lowly a transmission’s last byte, the BLAST rise along may use in symbolizing a data transmission completion. After a LCLK cycle, PLX9054 pulls the low LHOLD 熞 park sign to the local bus master control power, hereafter, local the bus arbitration responds 9054 LHOLD signals, and pulls low LHOLDA to take back local the bus master control power, by now local bus put in the idle condition. Here, PLX9054 takes local the bus master control power only applicant, so long as proposes the main line to apply, local the bus arbitration immediately the sound will apply.
1.2 HPI mouth design requirements
The HPI mouth is one kind of data width is the 16bit parallel port (C64** in series DSP, HPI mouth’s data width achieves 32bit). Through the HPI mouth, the main engine may carry on the operation directly to the CPU memory space. In C621*/C671* in series DSP, has not kept the special EDMA channel to carry out the HPI mouth accessing operation, but is connects the HPI mouth the internal address to produce directly on the hardware, thus enhanced to the interior storage space access speed. The HPI mouth interior has joined two eight level of depth read-write cushions, may carry out the address from the read-write operation which increases, enhances the read-write operation the volume of goods handled. The HPI mouth has provided the standard 32bit data interface for internal CPU, simultaneously has also provided an economical 16bit connection for the exterior main engine, therefore speaking of the exterior main engine, each time the read-write must carry out the geminate 16bit operation.
The HPI mouth interior has three registers, respectively is controls the register (HPIC), address register (HPIA) and data register (HPID). These three registers may by the main engine visit, the main engine carry out every time directly one time must to control first visit to CPU interior storage space the register and the address register read in the corresponding value, then can carry on the read-write operation to the data register. The HPI mouth’s exterior connection is 煟 guarantees the load sea by data bus HD an item of 刂 pu lotus root to throw the mallet mulberry these control signal by 犚 approximately rake huai rice polishings Zhong Meiwei fang chuo Tu 刂 weary decayed tooth school Shan Yongjie the concrete type to be as follows:
HCNTL[1:0]: Controls HPI the operation type;
HHWIL: Half character confirmation input, “0″, “1″ expresses the character transmission first-and-a-half characters and the second-and-a-half characters separately;
HR/W: Reads/writes the choice;
HRDY: Ready state symbol;
HINT: The interrupt symbolized that DSP proposes the interrupt to the main engine;
HAS: Difference address/data multiplying main line’s data and address;
HDS1, HDS2, HCS: The data selection input, three coordinations may use in producing HPI interior gating signal HSTROBE:
HSTROBE = [NOT (HDS1 XOR HDS2)] OR HCS;
Writes the HPI mouth regarding one operation, should first enable HCS, changes HDS1 or HDS2, may cause the HSTROBE signal to have a drop along, the HPI mouth 煟 guarantees the sea in this drop along sampling control signal HCNTL to suffer 牎ⅲThe decayed tooth decayed tooth wishes Sang Tanting decayed tooth remote W, simultaneously while enables HCS the fan to leave HRDY, causes the main engine to enter the waiting status, has the drop until HRDY along, indicated that HPID already clear spatial, may receive the recent data. This time HSTROBE also will have a rise along, and sampling HD 煟 guarantees the load sea by 犐 is the neon according to and sends in it HPID, completes the first-and-a-half characters read-. Regarding second-and-a-half character read-, because 32bit HPID was already clear spatially, may the direct write data, not appear has not prepared the good situation, therefore HRDY has maintained for low, reads in same as the first byte, this operation also in the HSTROBE drop along the sampling control signal, and sends in HPID in the HSTROBE rise along the sampled data main line HD[15:0] data, completes 32bit the write operation.
Figure 3
Regarding reads HPI the operation, when HCS is effective, and in the main engine does not use the address when increases the way reads the operation from the HPID execution (case1), HPI will produce the electric circuit to the dummy home address to deliver to read the request, the HCS drop along may cause HRDY to become the high level, will have the data which until the dummy home address the electric circuit will request to write down HPID, HRDY to become the effective condition, this time in data line data for read-out data, moreover this data will maintain effectively until the HSTROBE rise after the sampled data about 10ns. Because when second time reads the operation starts, the data already appeared on HPID, therefore, the second-and-a-half characters will read the operation not to meet have not prepared the good situation; In HPID by address when increases the way carries on reads the operation, HCS in the entire many byte’s transmission process throughout maintains effective, once completes the present to read the operation, the next address’s data is taken out immediately. Now therefore, after completing reads the operation the second-and-a-half character transmission, (in the HSTROBE second rise along), along (through will change HDS1 or HDS2 by the HSTROBE drop produces) the fan to leave the HRDY signal, uses in instructing that HPI is being busy with the data the pre-read.
Figure 3 is HPI reads, writes the succession chart, a here HAS direct high level.
2 designs realize
In this system the CPLD function is mainly completes local between the bus end and the HPI port the control signal and data bus’s connection, and guarantees the data transmission the reliability. Is obvious through above to local bus and the HPI read-write succession’s analysis, some essential signals, like HCS, READY, the HRDY succession design is very important, in fact, the entire CPLD design’s primary mission also centers on these signals the design to launch.
Figure 4
HPI which by HCS, HDS1 and the HDS2 combined action produces mouth interior signal HSTROBE rise along with drop along, the positive governing is sending in the HPI port’s data signal and the control signal, moreover the HSTROBE change speed had decided data transmission’s speed, thus it can be seen, this signal is a very essential signal. Here HCS signal takes the byte transmission symbol signal, it maintains effective throughout in a data transmission’s process. But after data transmission conclusion, pulls high HCS then controls the HRDY signal, makes it to restore to the original state, thus prepares for the next time read-write operation. When design, in available HDS1 or HDS2 meets fixedly to the high level, another uses for to control HSTROBE to have the rise along with the drop along. Author when design meets the high level fixedly HDS1, and has logic by ADS and the HRDY signal to control the HDS2 signal. When HRDY is in the invalid condition (i.e. the HPI port has not been ready), the HDS2 signal is invariable, not sampling any signal; But when HRDY is effective, the HDS2 signal with the ADS signal maintains consistent, and in ADS drop along sampling control signal, in rise along sampled data signal. Moreover, after a transmission started and the conclusion, HDS2 must maintain for the high level.
Regarding other control signal (for example height byte sign signal HHWIL), because they are along with the HSTROBE rise along the appearance has 0 and 1 alternate change unceasingly, therefore, available HDS2 produces HHWIL as clock input’s two frequency dividing circuit; But local bus application answering signal LHOLDA, then may by the LHOLD signal after a LCLK detention outputs the production; HCNTL[0:1] meets two address wires, in order to controls by the upper formation driver visit to HPI mouth interior different register’s, and meets the phase reverser by LW/R to produce R/the W signal. Its schematic diagram as shown in Figure 4.
3 concluding remark
This article provides this design method undergoes the actual run test, may guarantee between PLX9054 and the DSP reliable connection, and the logical relation is simple. Because the data line may be completely independent outside CPLD the direct connection, but saves the cost effectively, thus has the high use value and the economic value.
