One kind based on CPLD data acquisition control panel’s design
August 7, 2008 – 5:06 amAbstract: In view of many kinds of gathering signal type, designed one kind to use CPLD to realize signal function and so on gathering control, signal processing, communication and output control compound data acquisition control panels, and has analyzed its related application performance.
Key word: CLPD EPP connection encoder data acquisition
In needs to gather the multi-channel simulated signals, the switching signal, the frequency (counting) the signal as well as the encoder signal and so on the data acquisition application, the use general board card constitution computer observation system is feasible, but regarding the product batch application, its cost and the overall performance cannot be satisfying. The technical mature CPLD chip’s application, might function collections and so on logical control, data signal processing in a body, cause formerly to need well to use the duty conformity which many singleboarder cards could complete in the identical gathering controller, thus enhanced control system’s reliability effectively, reduced the observation system to realize the cost.
This article designs one kind based on the CPLD data acquisition control panel. It can realize functions and so on signal gathering and control, signal processing, communication and output control.
1 overall project design
This private data gathering control panel takes the master-control unit using CPLD, the unification coordinated channel cut and the digital signal processing, realizes the data acquisition and the connection transmission logical control. This data acquisition control panel altogether has four type signal inputs and one kind of switching signal quantity output. Figure 1 gives its basic hardware module composition.
Using the CPLD resources and the unique feature is this design core. In order to enhance the encoder input signal the resolution to be tall and slender, necessary designs a four doubling circuit, and designs a pulse static state counting circuit behind the channel, causes the input signal transformation is the 8bit signal hangs receives on the gathering board main line. The Chinese red army soldier simulator input mainly depends upon CPLD to realize the channel cut and a/D gathering, the sampled data also parallel enters the main line by the 8bit signal. Considered the enhancement counting precision the request, to a two group frequency input signal design dynamic counting circuit, has caused the counting value through the main line read-out. The I/O hand-off control, the EPP interface circuit and so on presses certain logical request to use the identical CPLD part to realize. So may make the hardware circuit to be very simple, and is advantageous in the superior machine programming realizes.
2 data interfaces
According to the IEEE1284 standard, in the standard parallel mouth (SPP), the enhancement parallel mouth (EPP) and the expansion parallel mouth (ECP) in three kind of patterns, the EPP pattern both has the bidirectional data transmission function, and has the high data transmission ability, and the programming operation is relatively easy, most suits in the data acquisition system uses.
Considered from the hardware design angle that one of EPP connection’s major functions is the data upload which gathers for the microcomputer or the stop-go control order downloads to gathers the control panel (data stream to correspond 8bit data port); Two are realizes between the hardware interface signal communication handshake (control state to correspond other I/O port). The EPP agreement has defined four kind of data transmission elementary operation eo: The data reads, the data to write, the address to read, the address to write. When work first reads in the I/O lock to save the address is the module operation I/O address, then carries on the corresponding read-out or the write operation. If does not need the I/O address substitution, then no longer carries on the I/O address lock to save the operation. Under the EPP pattern altogether defines 17 holding wires, besides 8 bidirectional address wires and data multiplying line, but also has output control holding wire WRITE, DSTROBE, ASTROBE, INIT, WRITE, DSTROBE and ASTROBE use in expressing the data read-write operation. WRITE is low when expressed carries on the operation, DSTROBE is the low expression carries on the data manipulation, but ASTROBE is low, then indicated that carries on the address operation. The EPP INIT signal uses for to reposition the printer, this design uses for to initialize the electro-optical encoder’s initial counting value. In addition has five condition holding wires. The WAIT signal sends out by the peripheral device, the high level expressed carries on the read-write operation, the low level expressed that the operation completes. But this design has not used this signal, because front three read-write signals have definitely been able to satisfy the request. MAX197 data conversion conclusion signal EOC connected and mouth SELECT on-line, when the main engine inquired the SELECT line for low, expressed that a A/D transformation ended, might read the transformation result. Other three condition line vacant achievement spare.
Figure 4
According to the IEEE1284 standard to the EPP pattern’s address, the data read-write operation’s stipulation, may use Figure 2 logical organization to realize the address to write, the data separately to write with the data reads. In Figure 2, in input signal’s STB expression writes a letter the number, ASTB expressed that the address writes a letter the number, DSTB expressed the data writes a letter the number; In the output signal the Add_WR expression address writes a letter the number, the high level to be effective, Add_WRN expressed that the address writes a letter the number, the low level to be effective, Data_WR expressed that the data writes a letter the number, the high level to be effective, the Data_WRN expression data writes a letter the number, the low level to be effective; Data_RD expressed that the data reads the signal. So the design goal is enables this connection to adapt each logical component’s operation request conveniently. Figure 3 gave has used the MAXPLUS software to carry on the simulation to the above logical signal the operation succession profile.
The EPP pattern may establish in superior machine BIOS or through writes the ECR register direct establishment (parallel adapter base address is 0X378H, I/O port address is 77AH).
Figure 5
3 encoder signal processing
Regarding the encoder input signal, has A in view of the increase type electro-optic encoder’s output, the B square-wave quadrature signal, moreover the two foreword is decided in the encoder is reversing the direction, has designed one kind of four frequency multiplications and sentences to the electric circuit, as shown in Figure 4.
In Figure 4, the CLK signal from the independent vibration source, its frequency is higher than above encoder maximum output frequency four times, but is not suitable excessively high, in order to avoid causes in the CPLD internal structure questions and so on signal competition. INA and INB respectively be encoder input A signal and B signal, CNT_UP and CNT_DN respectively be output clockwise frequency multiplication signal and reverse frequency multiplication signal. In order to guarantee that the encoder is in any corner position to be able the readout, the encoder frequency multiplication signal to count the digital way output finally reliably by the 16bit static state, CNT_UP and CNT_DN takes the following static state counting circuit separately “Canada” and “reduces” the counting input signal end. In the definition rotation angle ≤6×360° situation, counts the numerical code regarding 16bit, the counting circuit permission most important matter value is 65536, the counting value may according to the height eight rank two read-out. In order to enhance the encoder operational reliability, may also consider that carries on the gray code transformation. Figure 5 what gives is Figure 4 electric circuit’s signal simulation profile.
4 frequency measurements
Regarding the frequency input signal, uses and so on precision frequency measurement method survey frequencies. This method in the actual strobe time for was measured that the signaling frequency integral multiple under the condition, to measures when the signal counting is produced ±1 the character error to be possible to eliminate completely, and may cause the entire frequency region maintains the constant test precision.
Figure 6 has given and so on precision measure schematic diagrams, its survey principle is: First gives the strobe opening signal (the initialization gating signal SWITCH rise along), this time counter CNT1 and CNT2 do not start to count, but when was measured when signal SIGIN rise along arrival, the counter only then starts to count truly. After period of time, the pre-placed strobe closure signal (the gating signal SWITCH drop along) when arrives, the counter not immediately stops the counting, but when was measured signal SIGIN rise along arrival when only then finished the counting, completes a measuring process. This time may read out counter CNT1 and CNT2 counting value OUT1 and OUT2 separately, with was measured that signal SIGIN counting value OUT2 divides standard signal CLK counting value OUT1, was multiplied by the standard signal CLK frequency value to obtain again has been measured signal SIGIN the frequency value.
When use for the enhancement measuring accuracy, reference signal CLK may use the high accuracy the clock source, because to the clock source and was measured that the signal synchronization counting, the counting interval length will not affect the computed result. Figure 7 has given and so on precision frequency measurement law signal simulation oscillograms.
Figure 7
5 A/D switches and I/O hand-off control
Regarding the simulator input, uses 12bit MAX197 to take a/D signal shifter. This control word component work’s unit process is: First selects MAX197 by the address bus, then always reads in the analog channel control word through the data to the MAX197 interior register. This control word had decided elects channel number, channel input voltage scope, polar as well as internal or exterior triggering gathering way and so on. For example, the input voltage scope for the bipolarity, the internal triggering gathering way, the first channel, should read in 16 enters the system to count 48H, but reads in 4FH to the eighth channel. After the control word reads, MAX197 starts the channel switching immediately, after passing through approximately 10μs, transformed finishes. The transformation result lays aside on the data bus, first set at to lowly its high low position cut foot HBEN, this time the data bus first reads the result low eight, then sets at HBEN is high, then result high four place MAX197 on the D0~D3 mouth. Simultaneously sets at foot INT is low, informs the controller to transform completes. The MAX197 transformation result uses the complement representation, the highest order is a sign bit.
In this system also has the Chinese red army soldier switch quantity input output function hand-off control. These two kind of function distinction CPLD interior 74244 and 74373 realize. The interface logic and as shown in Figure 8. Exterior connection transmitted light pair isolation input output. The switch quantity reads in the order is selects first by the address bus 74373, then reads in the corresponding order character. Data quantity read-in and this similar. The concrete control signal gives by the EPP main line read-write logic.
6 actuate the software to realize
Considered NT Corporation LabView environment presente in figures and diagrams programming example, easy to realize and so on characteristics, (DLL) unifies through the design dynamic link function storehouse with the direct port operation realizes the gathering board hardware to actuate. In the programming process, produces DLL first using VC , then uses the CLF node in LabView to transfer DLL. Regarding the direct port operation, uses in LabView “In Port” and “Out Port” the node, realizes the operation to the port. Certainly, for easy to operate in order to, may also the I/O hand-off control, the encoder, A/D hardware unique functional design special-purpose modules and so on data acquisition, counter supply the LabView direct presente in figures and diagrams transfer.
Gathers control panel’s above hardware module project design, may use the suitable scale CPLD to realize. This act besides cost advantage, but also has the volume to reduce, merits and so on hardware integration rate enhancement, also has created the condition for the enhancement gathering reliability. CPLD each logical function design, because has the function formidable simulation software tool, design process fast highly effective also self-evident. The above design was actually already using to observe and control in the equipment to put into the application, in carries in the FIFO situation without the board, a/D speed may achieve above 40kHz; Has the board to carry in the FIFO situation, a/D speed may achieve a/D gathering part nominal upper limit. The EPP port can definitely satisfy the board to carry the functional module each kind of data transmission request. Through the scene feedback’s situation, gathers controller’s industry environment resistance to interference and the movement stability good behavior.
