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—In the modern data acquisition and the processing system, ISA, EISA, MCA and so on expand the main line to be unable to adapt the high speed data transmission request, but the PCI local bus becomes the majority system’s mainstream main lines by its outstanding performance-to-price ratio and the compatibility.
PCI main line characteristic
—PCI main line width 32, may promote to 64; Highest operating frequency 33MHz, supports the burst working, causes the transmission speed to be higher; The low direct access retards (to is subordinated register from main line’s master control register to write visit detention is 60ns); Processor/memory subsystem ability is completely consistent; Concealment central arbitration; The multiplexing architectures reduced the base pin number and the PCI part; For in ISA, EISA, MAC system’s PCI expands the exhibition board, reduced user’s development cost; Can dispose automatically to the PCI expansion card and the part, realize the equipment namely to insert namely use; The processor independence, does not rely on any CPU, will support many kinds of processors and the future high performance processor; Supports 64 bit addresses; The multi-master controls permit any PCI main equipment and carry on the point-to-point visit from the equipment; PCI provides the data and the address parity check function, has guaranteed the data integrity and the accuracy.
PCI connection development present situation
—At present develops the PCI connection to have two ways roughly; first, uses the special-purpose PCI connection chip, may realize the complete PCI master control module and the object module interface function, the complex PCI bus interface will transform into the relatively simple user interface. So long as after the user designs transforms the bus interface then, reduced the development cycle, the shortcoming is the user possibly only uses the part PCI interface function, like this has created certain logical resource waste, also lacks the flexibility, very possibly increases on the board the module, causes the product cost increase with reliable reduction. Second, uses the programmable component, uses FPGA the merit to lie in its nimble programmable, the first PCI connection may rest on inserts the card function to carry on the optimization, but does not need to realize all PCI function, like this may save system’s logical resource. Moreover, the user may insert PCI in the card other user logic and the PCI interface logic integration on a chip, realizes the compact system design. When system upgrade, only need carry on the logical design to the programmable component, but does not need to renew the PCB domain. Now already had more and more users to use programmable component like FPGA, CPLD and so on to carry on the PCI equipment’s development.
—This article elaborates the PCI connection controller is takes a transformation connection of work between the PCI main line and the subscriber’s equipment, may also think that its major function is a bridge role, completes information transmission between the subscriber’s equipment and the PCI main line’s.
PCI connection design
—In the PCI board card’s design, the core design has the sequential control and the disposition space two parts. The sequential control had guaranteed the board card could according to the normal PCI sequential working, the disposition space segment guarantee the board card namely inserted namely uses the function. When carries on the FPGA design this design use’s software is Altera MAX PLUSII, the development chip is EPF10K20RC240-3.
* PCI connection disposition space realization
—The PCI main line has defined 3 physical address space, respectively is the memory address space, the I/O address space and the disposition address space.
— The disposition space is the PCI unique one kind of space, its goal lies in provides a set of suitable disposition measure, causes system disposition organization which it satisfies present and may foresee. The disposition space is a length is 256 bytes, and has the specific record structure address space, may when the system from lifting visits, may also in other time visit. This space divides into the first area with the equipment related area two parts, the equipment only need realize in each area essential and with it related register. The disposition space’s base register provided one kind to assign the storage space or the I/O space mechanism for the equipment. Operating system in start time must judge in the system to have in how many memories, system’s I/O equipment to need how many address space, then the basis obtains the result, disposes system’s storage space and the I/O space automatically, realizes the equipment irrelevant management. In this design, these read-only disposition register through hardware segment to corresponding value, thus does not take the great unit. Through disposes the register, disposes the software to be possible to understand the goal equipment’s existence, the function and the disposition request.
—(1) manufacturer ID: This 16 read-only registers have defined equipment’s production manufacturer, may use MACH chip initial production manufacturer - AMD Corporation’s ID value 1022.
—(2) equipment ID: This value distinguishes its product by the production manufacturer assignment, may for except in 00000000H and the 0FFFFFFFFH random value.
—(3) orders the register: This register controlled the equipment to respond the PCI visit ability. The position 1, 6, 8 are realized in this design. This design requirements realize visit to storage space, the position 1 establishment are 1, then the equipment responds PCI to visit to the memory; The position 6 have controlled the equipment to the parity check wrong response; When the position 8 by the establishment are 1, the equipment can actuate the SERR line, 0 pieces forbid equipment’s SERR output driver. After here works as system reset, the position 1, 6, 8 by the establishment are 0.
—(4) condition register: This register has recorded the PCI dependent event’s information. In this system, the position 9, 10, 11, 14, 15 are designed realize. The position 10∶9 for unit select (DEVSEL#) fixed time, 00B is the idling speed, 01B is the medium speed, 10B is fast, 11B retention. This design these two by the hardware segment are 01B. When the goal equipment is defeated, the position 11 by the establishment are 1, when has the systematic error the position 14 set 1, has when the parity check mistake the position 15 set 1.
—(5) base register: This register uses for to map equipment’s memory address space, with the device address space size corresponding low position by the compulsion is 0, therefore in the disposition writes in the transaction, disposes the software through to write to this register’s all positions 1, then reads out this register’s value to decide again the equipment memory takes address range. The position 0 use for to define the equipment is the memory mapping or the I/O mapping, in this design, the position 0 supposes to lower take indicates the goal equipment as the memory mapping.
If needs 256 byte storage spaces, disposes the software to read in 0FFFFFFFFH, this equipment sends out 0FFFFFF00H, but disposes the software to read in base register’s value the result which deals with this equipment’s 0FFFFFF00H is the base address value once more, if disposes the software to read in the 0CD000000H base address value is 0CD000000H once more.
—(6) kind of code register: This 24 read-only registers use for to explain equipment’s basic function and its programmable connection. Here, this register by the compulsion is 018000H, namely equipment for large capacity storage control unit.
—(7) first type register: This read-only register’s position 0~6 defined the first form, the position 7 explained the equipment for the single function multi-purpose. The first type 1 is the PCI-PCI bridge definition, the first type 2 pieces use in PCI the CardBus bridge. The register is 0 demonstrates in this design by the compulsion it for the single function equipment, and the first type is 0.
* sequential control
 —Uses the state machine model in the sequential control procedure to realize the different succession transformation. Each kind of order, the data exchange, the control carry on the work under state machine’s management. On the PCI main line’s signal is the multi-tasking, therefore, corresponds each condition to be clear about its execution the duty. These duties need to use the event which VHDL the advancement sentence describes occurs. In this design’s state machine has altogether used 6 conditions, it take from the equipment response condition as the basis, mainly take the DEVSEL# signal and the TRDY# signal’s condition as the basis. State machine as shown in Figure 1, corresponds the idling condition separately (this condition DEVSEL#, TRDY# and STOP# as well as other output signal for high-impedance state); The ready condition, DEVSEL# and TRDY# are the high level condition, DEVSEL# are the low levels, and TRDY# is the high level condition, DEVSEL# and TRDY# are the low level conditions; The operation conclusion condition (this condition caused DEVSEL#, TRDY# and STOP# maintains one cyclical high level). After this system receives the reset signal, carries on the replacement to the system, then changes over to the idling condition, in the idling condition the sampling main line, and rises according to main line’s change decision next clock after the state machine changes over to what condition, in these successions and the procedure use the signal is basic, and must, when carries on the development may according to need to increase the essential condition and the signal, VHDL is as follows to state machine’s description.
— type pci_state is (Idle, Ready, DevTrdyHi, DevLoTrdyHi, DevTrdyLo, OprOver);
signal c_state: pci_state;
—Idle is the idling condition; Ready is the ready condition; DevTrdyHi expressed that DEVSEL# and TRDY# are the high level conditions; DevLoTrdyHi expressed that DEVSEL# is the low level, and TRDY# is the high level condition; DevTrdyLo expressed that DEVSEL# and TRDY# are the low level conditions; OprOverr expressed the operation conclusion condition.
The procedure is as follows.
process(pci_rst, pci_clk)
begin
if pci_rst = ‘0′ then
c_state <= Idle;
elsif pci_clk’event and pci_clk=’1′ then
case c_state is
when Idle=>
if pci_frame_l=’1′ and pci_irdy_l=’1′ then
c_state <= Idle;
elsif pci_frame_l=’0′ then
c_state <= Ready;
else
c_state <= c_state;
end if;
when Ready=>
if pci_frame_l=’1′ and pci_irdy_l=’1′ then
c_state <= OprOver;
else
c_state <= DevTrdyHi;
end if;
when DevTrdyHi=>
if pci_frame_l=’1′ and pci_irdy_l=’1′ then
c_state <= OprOver;
else
c_state <= DevLoTrdyHi;
end if;
when DevLoTrdyHi=>
if pci_frame_l=’1′ and pci_irdy_l=’1′ then
c_state <= OprOver;
else
c_state <= DevTrdyLo;
end if;
when DevTrdyLo=>
if pci_frame_l=’1′ and pci_irdy_l=’1′ then
c_state <= OprOver;
elsif pci_frame_l=’1′ and pci_irdy_l=’0′ and trdy_l=’0′ then
c_state <= OprOver;
else
c_state <= c_state;
end if;
when OprOver=>
c_state <= Idle;
when others=>
c_state <= Idle;
end case;
end if;
end process;
—Next step should list the concurrent event which each condition corresponds, writes the related advancement. The advancement sentence is a parallel sentence, the specific behavior which it defines the advancement activates when is going to carry out. For example, when the Ready condition, must judge the address message which sends from the main equipment side with to be whether same from the device address, must therefore write the address comparison advancement.
— address_compare:process(pci_rst, pci_clk), the primary coverage is to the address decoding, the judgment address whether from equipment space, if may make the next step in this space the movement, otherwise does not make other movements.
 —May obtain the entire design mentality from the above parsing process to be as follows: In clock’s rise along sampling FRAME#, address and order, if FRAME# is effective, then decoding address and order, if the main line order is 011x, and on main line’s address in the goal address range, indicated that this is to this equipment’s memory operation; Or the main line order is 101x, and the IDSEL signal is effective, indicated that this is to this equipment disposition space operation. In these two kind of situations, is reads the operation according to the main line order’s last determination or writes the operation, effective DEVSEL# and the TRDY# signal, starts the data transmission; And in the transmission process sampling FRAME# and the IRDY# signal, confirmed that the last data cycle, invalid DEVSEL# and the TRDY# signal, finished the data transmission.
— Through the above design, under the MAX PLUSII environment group of analogue result as shown in Figure 2.
Concluding remark
This article gave has used FPGA on the PCI main line the technical design PCI bus interface the design proposal. May makes using this technology own algorithm technology and some softwares the hardware, solidifies to the card, like this already raised the running rate, may also protect the intellectual property rights.
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