Abstract: In flight vehicle’s in and so on missile, spacecraft development test flights, usually must gain the system internal active status parameter and the environment parameter through the telemetry, to complete the different task, needs to gather the different signal, utilizes the different modulation system. The article introduced realizes some detector test and the signal processing system with the DSP CPLD pattern to signal gathering, and completes PCM using the DSP formidable function and so on a series of functions the method.
Key word: DSP; PCM; CPLD; Information acquisition
1 introduction
The information acquisition mainly includes the signal and data gathering, the memory, processing and the control. It to was measured first that physical analogue quantities and so on object temperature, pressure, current capacity, displacement, angle, voltage carry on gathering, the record, and transforms it into the digital quantity, then further carries on the transformation, the memory, processing, the record and gathering again. The multi-channel signal transmission’s method has the frequency division system, the code system, the time division system and so on. And the time division system telemetering is differentiates the telesignalization by the different time sector. With the sampling pulse scope reflected that was measured the parameter the method is called the pulse amplitude modulation (PAM); With the sampling pulse width either the position reflected that was measured the parameter the method is called the pulse width parameter (PDM) or the pulse position modulation (PPM) 牰, if with a group of coded pulse anticlutter system reflected that is measured the parameter, is called the PCM (PCM). At present in missile, in spacecraft telemetering, what uses are most is PCM, next is PAM.
The PCM telemetry system is one kind of commonly used telemetering device, it may gather the multi-channel data and carry on the correspondence transmission and the data processing, its multi-channel data acquisition equipment is editing. Editing mainly uses in controlling gathers each data channel data the succession, and adds on the frame synchronization code to form certain form the data, carries on and/the string transformation again forms the serial data stream to deliver modulates the equipment to supply the transmission. Figure 1 is a typical PCM frame form schematic drawing.
2 information acquisition system’s hardware realizes
2.1 information acquisition system’s constitution principle (typeface establishment)
Basic information acquisition system’s structure as shown in Figure 2. Its core part is the frame form former (has ROM and the CPU two kinds), this former presses the succession to issue the gathering order and the address at the same time to each part, on the other hand collects each kind of data and adds on the synchronous code group and other information code group, thus forms is advantageous for the transmission the data frame form. This design realizes its function directly with DSP.
Figure 2 the multi-channel simulation gate (popular name exchange) selects two 16 to choose 1 ADG426 chip to carry on the unitized design, constitutes conforms to the request multiplex gate. The frame form former sends the address takes on-off control signal. The pre-amplification electric circuit selects low noise amplifier, guarantee system to weak signal non-distorted enlargement survey. Amplifier’s function is provides the high input impedance for the input end, by reduces the parameter error as far as possible, simultaneously provides the enough enlargement factor for the signal, causes to measure that the signal maximum value achieves a/D full scale division level. Because simulated signal’s input level stipulation is 0~5V, therefore, time survey exchange signal, should raise the central value 2.5V, uses AD9240 to be possible to satisfy its request very easily.
The multi-channel digital parameters waited for first in the connection, when corresponding sampling time slot arrival only then external digital quantity synchronization insertion data frame form. The time division system telesignalization’s synchronization and the time slot relations are very strict, once had determined after the transmission signal and the operation requirements symbol speed rate and frame form, all time slot form and the synchronized relations fixed down. Regarding the external belt synchronization symbol’s entire code group block data (is not detachable character), the PCM frame form may use the window to receive. “Piles up one on top of another” the external block data in advocates in the PCM frame form window position to be called the asynchronous inserting form. When execution, the receiving end defers to first advocates the PCM synchronization to symbolize that found the window position, then by the external data’s group synchronization symbolized that the code group obtained this block data to compose the rule. Obviously, a PCM entire frame may open many windows. The data recording instrument’s replay data inserts on the available this kind of asynchronous form to the PCM frame form in transmits.
2.2 component choices
ADG426 has 16 inputs and a public output monolithic CMOS simulation selector, may serve as in system’s analog switching gate. May through 4 binary address A0, A1, A2 and A3 decided that which group chooses. ADG426 has the chip level (monolithic level) the address and the control valve, is very easy and the microprocessor connection.
ADG426 uses the enlargement mode LC2MOS craft, has the low power loss, the high shutter speed and the low impedance characteristic. The low power loss to the battery power supply system is very practical. When is at the clear condition, each channel may conduct two directions equally the data, moreover also has one to surpass the power source scope the input signal. When is at the abruption condition, will be higher than the power source scope the signal level to block. When transforms channel’s instantance, before all channels transform the flash, they assume the disconnect state. In design, when the transformation is the digital input, its intrinsic property is pours into by the smallest transient state low electric charge.
A/D switch selects the sampling rate is 10MSPS 14 AD9240. AD9240 has the high performance low noise sample maintains the amplifier and the programmable voltage datum. Simultaneously may also choose exterior reference voltage, satisfies in the use to direct current the precision and the temperature drift demand. This component uses the multistage difference running water line structure, and has the digital output error correction logic, thus may guarantee that not loses the code in the entire temperature range. The AD9240 input has the very high flexibility to be possible for the image, the correspondence, medical and the digital gathering system provides the convenient connection. Actually when the differential input structure may provide the single end input and the differential input connection. Takes a sample maintains an amplifier 煟 cherry decayed tooth grain of 犚 meal type is suitable for the multiplexing systems, this system may transform the full scale division level in the continual channel, even may surpass the Nyquist speed to the single channel input frequency the signal to carry on the sampling. AD9240 in the differential input pattern, its SHA can achieve the fine dynamic characteristic, and may surpass fixed 5MHz the Nyquist frequency. Uses the single clock input to control all internal conversion cycle. The data output uses the direct binary system output format. When surpasses the transformation scope, the available OTR signal instruction overflow, at the same time this signal may also judge the result is the top digit overflow or the low position overflow.
AD9240 transformation clock 5MHz, every 4 transformations only take a valid data, therefore the available 1.25MHz clock makes DMAR. Reads in the first four cycles through the DMAR signal the second transformation valid data, may avoid ADG426 the selector 120ns switching time the influence.
AD9240 the switch inner tube 2.5V reference voltage, may select the single end conductive coupling method the signal input to AD9240. The data lock saves, then completes by CPLD. The lock saves clock and the DSP DMAR same cycle, i.e.: After the CPLD lock saves, may input DSP immediately through the DMA way.
TigerSHARC DSP chip ADSP-TS101 is a section of high performance static exceeding the allowed figure quantity processor, specially carries on the optimization for the big signal processing duty and the correspondence structure. This processor the very wide memory bandwidth and the double operation module will combine in together, thus has established the digital signal processor performance new standard. Its main performance includes:
* instruction execute speed 300MHz, instruction cycle 3.3ns.
* internal has 6M position SRAM, divides into three modules, each module is connected through the independent address bus and the data bus, therefore may simultaneously carry on the visit. Intranuclear has the pair of operation module, each operation module contains ALU, a multiplier, a shifter and a register group. Intranuclear has pair of integer ALU, may provide the data addressing and the indicator operating function.
●I/O the part including 14 DMA channels, 4 chain street intersection and the SDRAM controller and so on, on the piece the arbitrated system may also constitute 8 Tiger SHARC the DSP sharing main line seamless connection multi-processor system.
ADSP-TS101 has three set of independent address buses and the data bus. The internal data main line width expansion is 128, the exterior data bus width may expand is 64.
The ADSP-TS101 synthesis handling ability is outstanding. Its peak value operational capability may reach 1600M Flops/s,1024 plural number FFT only to need 32.78μs, external bus’s data transfer rate may reach 800Mbytes/s. Each chain street intersection’s data transfer rate is 250 Mbytes/s.
2.3 succession relations and partial hardware circuit
Through clock’s rise when saves along the lock, its succession relations as shown in Figure 3. Shown in Figure 4 is this system’s partial hardware schematic diagram. When design also used in Altera Corporation CPLD series EPM7128.
3 software designs
3.1 forms
In China’s certain stipulations, to protect the PCM remote control data, uses two kind of remote control expansion frame in the PCM telemetering, namely the real-time switch order and the serial data pour into the frame. These two kind of remote control frame’s behind may attach a length is 8m (m=1,2,3 ……) the bit sequence uses in the data the protection. Specific as shown in Figure 5.
After this system 熜 the lotus root moves the clothes, may defer to reference signal the cycle to carry on minute frame processing, what the procedure each time processes is on a sampled data (data processing time delay 1), then again according to computed result synthesis track signal; During processing data’s, may use the interrupt output previous to calculate the track signal (track signal output time delay 2).
Supposition reference signal as shown in Figure 6, that uses the zero crossing detection to be possible to obtain the plus and minus zero crossing time, but reference signal’s zero crossing is not sometimes only, therefore may change the zero crossing detection some fixed level check.
In the zero crossing time, may produce hardware interrupt IRQ0 by the zero crossing detection electric circuit, the interrupt response procedure first records the current buffer length L, then carries on the buffer cut. The supposition cuts the buffer Buffer (I) (I=1,2,3,4), hereafter the sampled data selects the DMA method to put in Buffer (I). Then, 4 buffers will defer to 1->2->3->4->1 the way circulation.
In negative zero crossing time, will produce hardware interrupt IRQ1 by the zero crossing detection electric circuit, then basis of calculation signal positive peak position N, (for clarity, Figure 6 different cycle’s N separately uses N1 and the N2 expression), defines M is when the IRQ1 interrupt current buffer length, then N1=M/2. Between the neighboring two peak value’s data is a data, in Figure 6, between N1 and the N2 data is a data.
Because reference signal’s frequency is unstable, therefore cannot use the fixed length the buffer. For ease of the addressing, gathers the data buffer the length to decide as 1024. Because a complete data will surmount two buffers, simultaneously to process the goal to surmount two data the situations, may decide as the sampling buffer number 4, an achievement current gathering data DMA transmission goal, other three achievement two complete data buffers.
Because altogether has 22 groups signals to need the sampling, the establishment buffer should have 22 groups, therefore, defines 0~15 is the midwave signal, 16~20 are the shortwave signals, 21 are the reference signals, 22 for unlocking signal.
3.2 synchronized questions
Besides the frame form, the time division system telesignalization’s synchronization and the time slot relations are also very strict the synchronized question which 熂 this says. Has the frame synchronization, the character synchronization, the position synchronization specifically and so on many kinds of forms. In digital telemetering (PCM) in system, what on the channel transmits is the binary system coded sequence, the insertion frame synchronizing signal must easy distinguish and the extraction, and should have the remarkable difference with the normal signal encoding, and can reduce the false synchronization and leak the synchronized probability. At present the commonly used frame synchronization code group has the Barke code group, the pseudo-random code group and so on. In fact a more basic synchronization is the clock synchronization (is also called road synchronization or position synchronization), is also requests the receiving and dispatching both sides data stream the clock strict synchronization. This system uses the reference signal which the CPLD docking receives to carry on processing by to take the frame synchronization the symbol.
4 concluding remark
Through the time division system, and the PCM high speed data gathering system which technology realizes with DSP the DMA has the very high signal-to-noise ratio, definitely may achieve the design requirements. In fact, this realizes the plan also to be possible to promote to the multi-channel gathering systems, but designs time should consider the performance-to-price ratio and the main line speed question.
