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—UART (i.e. Universal Asynchronous Receiver the Transmitter general asynchronous transceiver) is the widespread use serial data transmission agreement. The UART permission carries on full-duplex’s correspondence on the serial link.
—The serial peripheral device uses the RS232-C asynchronous serial interface, generally uses the special-purpose integrated circuit is UART realizes. Like chips and so on 8250, 8251, NS16450 are the common UART components, this kind of chip was quite already complex, some include many auxiliary modules (for example FIFO), sometimes we do not need to use complete UART the function and these auxiliary functions. Or designed uses the FPGA/CPLD component, then we might need the UART function integrated in FPGA. Uses VHDL the UART core function integration, thus causes the entire design to be more compact, to be stable and is reliable. This article applies the EDA technology, with realizes UART based on the FPGA/CPLD component design.
A UART synopsis
1 UART structure
 —UART mainly has by the data bus connection, the control logic, the baudrate generator, the transmission part and the receiving unit and so on is composed.
—The function including the microprocessor connection, transmits the buffer (tbr), the transmission shift register (tsr), the frame to have, the parity check, and transfers the string, the data receive buffer (rbr), the receive shift register (rsr), the frame to have, the parity check, the string to transfer and.
—Figure 1 is the UART model application.
2 UART frame forms
—UART frame form as shown in Figure 2.
 —Including the line idle condition (idle, high level), the outset position (start bit, low level), 5~8 bit data positions (data bits), the verification position (parity bit, may choose) and the stop position (stop bit, figure may be 1, 1.5, 2).
—This kind of form is realizes the character synchronization by the outset position and the stop position.
—The UART interior has the disposition register generally, may the layout data figure (5~8), whether to have the verification position and the verification type, the stop position figure (1,1.5,2) and so on establishments.
Two UART designs with realize
1 UART transmitter
—The transmitter every other 16 CLK16 clock cycle outputs 1, the order follows 1 outset position, 8 bit data positions (hypothesis data position is 8), 1 bit check position (may choose), 1 stop position.
—When can CPU toward the transmission buffer tbr write data, i.e. CPU must write the data to tbr when probably judge current whether can write, if does not sentence this condition, the transmission data will make a mistake.
—The data transmission is controls by the microprocessor, the microprocessor gives the wen signal, the transmitter acts according to this signal [7..0] the lock to save parallel data din sets out delivers buffer tbr [7..0], and [7..0] transmits the serial data through transmission shift register tsr to serial data out-port dout. Takes the symbol signal in the data sending process with output signal tre, when a data end of transmission, the tre signal is 1, informs CPU to load the recent data in the next clock.
—Transmitter port signal as shown in Figure 3.
—The introduction transmission character length and transmission order counter length_no, realizes the part VHDL procedure is as follows.
—if std_logic_vector(length_no) = “0001″ then
—tsr <= tbr; –The transmission buffer tbr data enters transmission shift register tsr
—tre <= ‘0′; –The transmission shift register spatial symbol sets “0″
—elsif std_logic_vector(length_no) = “0010″ then
—dout <= ‘0′; –Transmission outset position signal “0″
—elsif std_logic_vector(length_no) >= “0011″ and std_logic_vector(length_no) <= “1010″ then
—tsr <= ‘0′ & tsr (7 downto 1); –From the low position carries on the shifting output to the top digit to serial out-port dout
—dout <= tsr(0);
—parity <= parity xor tsr(0); –Parity check
—elsif std_logic_vector(length_no) = “1011″ then
—dout <= parity; Verification position output
—elsif std_logic_vector(length_no) = “1100″ then
—dout <= ‘1′; –Stop position output
—tre <= ‘1′; –The end of transmission symbol set “1″
—end if;
—Transmitter simulation profile as shown in Figure 4.
 2 UART receivers
—The serial data frame and the receive clock is asynchronous, transmits the data 1 becomes logic by logic 0 to be possible to regard as a data frame the start. The receiver must catch the outset position first, determined that the rxd input from 1 to 0, logic 0 takes 8 CLK16 clock cycle, is the normal outset position, then in every other 16 CLK16 clock cycle sampling receive data, carry input receive shift register rsr, final output data dout. Must output a data accepted flag marker data to receive.
—Receiver’s port signal as shown in Figure 5.
 —Realizes the part VHDL procedure is as follows.
—elsif clk1x’event and clk1x = ‘1′ then
—if std_logic_vector(length_no) >= “0001″ and std_logic_vector(length_no) <= “1001″ then
—–The data frame data shifts into the receive shift register by the receive serial data end
—rsr(0) <= rxda;
—rsr (7 downto 1) <= rsr (6 downto 0);
—parity <= parity xor rsr(7);
—elsif std_logic_vector(length_no) = “1010″ then
—rbr <= rsr; –The receive shift register data enters receives the buffer
—……
—end if;
—Receiver simulation profile as shown in Figure 6.
 3 baudrate generators
—The UART receive and the transmission defer to the same baudrate to carry on receiving and dispatching. The baudrate generator produces the clock rate is not the baudrate clock rate, but is baudrate clock rate 16 times, the goal is for when the receive carries on precisely the sampling, proposes the asynchronous serial data.
—According to the crystal oscillator clock which and the request baudrate assigns figures out the baudrate frequency division number.
—Baudrate generator simulation profile as shown in Figure 7.
 Three subtotals
—Through the baudrate generator, the transmitter and the receiver module’s design and the simulation, can realize the general asynchronous transceiver total module easily, and has the baudrate clock rate regarding the receiving and dispatching data frame to be able to change nimbly, moreover the hardware realizes does not need many resources, especially can insert nimbly to the FPGA/CPLD development. Carries on the design, the simulation in the EDA technology platform and realizes has the good superiority.
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