Abstract: Mega8 is a section of high performance, the low power loss, uses the advanced RISC simplification instruction, built-in PWM and a/D 8 monolithic integrated circuits, design the digital power amplifier cost with it to be not only low, the hardware is simple, moreover easy to realize each kind of extended function. In the article introduced how and new VMOS manages IRF7389 using AVR series monolithic integrated circuit mega8 to design the highly effective digital power amplifier the method, simultaneously has given the corresponding electric circuit schematic diagram, the procedure flow and the test result.
Key word: mega8; Digital power amplifier; PWM; AD8605; IRF7389
1 introduction
Digital power amplifier as a result of its efficiency high, easy and merits and so on digital sound source docking, but has more and more widespread application in the real life. It mainly contains two parts, Figure 1 is the digital power amplifier basic diagram. And the PWM transformation has two kinds approximately; first, simulates PWM, soon inputs simulated signal or digital signal after D/A carries on the comparison with the triangular wave, this kind of transformation must have frequency over a hundred kHz, the linearity to be good, Man Fu triangular wave, moreover must have simulates the comparator high speed, will otherwise affect the PWM profile after the demodulation profile, these will increase the cost and the design order of complexity (use integrate D kind of power amplifier or D kind of control chip regard as another matter). Second, digital PWM, soon inputs the digital signal or the simulated signal after A/D compares with the counter, namely replaces the triangular wave with the counting method, thus has avoided the distortion which the triangular wave misalignment causes. The same tradition’s analog form compares, the digital form has the design to be simple, the efficiency is higher, the anti-jamming is stronger and so on merits. But in the Atmega8 monolithic integrated circuit’s timer 1 may work in the PWM pattern, so long as it transfers to its AD in value in the PWM output comparison register then to complete the PWM modulation, realizes quite easily.
In order to raise the output, the majority D kind of power amplifiers actuate by the BTL way.
But regardless of is the simulation type or the digital PWM, BTL two group output signal choice also has two kind of plans, namely synchronism actuation and opposition actuation. The former when zero signal, its two group signal’s superimposition effect is zero nearly, but the latter in zero signal time, will superimpose will increase on filter’s voltage, certainly may reduce it through the revision filter parameter in the load pressure drop, but like this will increase the system power loss, will not be advantageous for the whole to realize. Therefore, this article selects digital PWM, and adopts the synchronism drive type to realize the digital power amplifier function, thus further reduced the static power loss, raised the efficiency.
2 hardware designs
This design’s hardware circuit divides into three parts, including the pre-amplification, A/D and PWM transforms, the power amplification and the filter and so on, its hardware circuit principle as shown in Figure 2. This system’s PWM frequency must modulate at least to the signal upper frequency (20kHz) above 5 times, can guarantee the tonic train signaling very good return to original state. If the operating frequency is 16MHz, then the PWM counting maximum value (will hereafter refer to as TOP) will be: fCLK-I/O/fpwm=16MHz/100kHz=160. In addition, a/D sampling value (biggest 255) must divide certain value to be able (hereafter refers to as OCR1A/OCR1B) as the PWM output comparison register the value, this will reduce AD obviously the equivalent precision. But must guarantee that the AD original precision and the PWM frequency, should enhance the crystal oscillator. After test: mega8 under 32MHz may also the normal work, this time the AD sampling value be possible to take the OCR1A/OCR1B value, this time’s PWM frequency is 32MHz/255=125.5kHz directly.
2.1 pre-amplifications
The pre-amplification part mainly by the AD Corporation’s low power loss, the low noise, the single power source, the axle is composed to axle input transmit amplifier AD8605 and the digital potentiometer. The AD8605 quiescent current only then 0.9mA (5V), the power source scope is 2.7V~5.5V, the band width is 10MHz. The digital potentiometer uses X9C102 has 100 stairs, the size for 1kΩ 熥 the plutonium]The gauze zheng towering oh luck it and AD8605 may compose the synchronism amplifier. Figure 2 R2 elects for 1kΩ, the enlargement factor may in adjust 2 to 250 between.
2.2 A/D and PWM parts
In this design’s A/D and PWM are complete through mega8. In the AVR family, Atmega8 is a very special monolithic integrated circuit, its interior integrated the large capacity memory and the rich hardware interface electric circuit, has AVR the upscale monolithic integrated circuit MEGA series complete performance and the characteristic, but because has used the small pin seal (DIP 28), therefore its price and low-grade monolithic integrated circuit quite, thus the performance-to-price ratio is extremely high, and has the ISP function, downloading is extremely convenient.
Figure 2
The Atmega8 monolithic integrated circuit function is complete, the connection is rich. It has 6 channel A/D, including 4 group 10 A/D and 2 group 8 A/D. But in the piece 3 PWM channel may realize is smaller than 16 willfully, as well as phase and frequency adjustable pulse-duration modulation output. In addition, in the Atmega8 each I/O pin uses the push-pull actuation, therefore not can only provide the big electric current actuation, moreover may also absorb 20mA the electric current. Atmega8 PWM has 3 kind of working patterns: Fast PWM pattern, phase adjustable PWM pattern and phase frequency adjustable PWM pattern. After and, both use the double stroke counter, therefore its PWM frequency only then fast pattern half. This article selects the first kind of working pattern. This pattern is 1 completes using the timer/counter, moreover the counter for one-way upward Canada 1, has added to TOP from 0×0000, when next counter impulse arrival resets, then starts from 0×0000 to add 1 counting again. When establishment to comparison matched output, when the counting value and the OCR1A/OCR1B value is being same, to outputs a comparison coordinate (to hereafter refer to as OC1A/OC1B) to carry on the setting operation 煹 rushes splits the value returns to time 0×00 from TOP, then to reset OC1A/OC1B. But when establishment reverse comparison output, its output just right and when cocurrent comparison opposite. Looking from two group PWM generating processes, two groups changes are at the same time, thus has avoided, because two groups time delays different cause extra loss.
2.3 power amplification part
The power amplification part uses two piece of IRF7389, each piece of built-in pair of VMOS tube, the N trench and the P trench’s breakover resistance respectively is 46, 98mΩ 煟 Zheng Qianying when sword towering 5V 牐 the peak power output is 30W. In addition, IRF7389 also built-in high speed restores the diode, can reduce the harmonic distortion. Figure 2 C17, C16 are the speed-up capacitors, may use for to improve the excitation waveform, take causes the VMOS tube to transform rapidly by the closure as the breakover, or transfers the closure rapidly by the breakover, achieves the reduction dead time, goal of the improvement output wave shape. Figure 2 R7, R8 are main the protective function.
3 software designs and system experiment
This system software by the AD interrupt service, the timer interruption service routine, the PWM procedure, the pressed key interrupt service is composed.
On after system electricity, the AD interrupt routine, the clock interrupt procedure, 
the PWM procedure first carry on the initialization, then carries on the volume in the program run preliminary stage the AGC control. Considered the person ear to receives the sound level the logarithm relations, amplifier’s gain designs the geminate number from 2 times to during 20 times to increase the way, but does not need the hand regulation enlargement factor, thus enables the output to guarantee based on this, causes the amplifier work at the linear area. The concrete process see Figure 3 to show. In the broadcast process, may transfer the interrupt subroutine through the pressed key to adjust the volume.
Atmega8 AD transforms when the conversion accuracy request is lower than 10, the ADC sampling clock may be higher than 200kHz, thus may obtain a higher sampling rate. Moreover establishes SFIOR in register’s ADHSM position to be possible to enhance ADC the clock rate. This system uses the ADC materials for internal reference power source and transforms the pattern continuously, and selects the ADC4 channel (precision is 8), the experiment obtains the conversion rate may reach 40kHz.
When PWM A, the B channel initialization uses the same working, zero input, A, B synchronism output. But works as when signal input, a channel’s pulse width increases, because this time B channel’s correlative value and A channel supplementary, therefore B channel pulse width reduction; When has negative signal input, a channel’s pulse width reduction, the B channel’s pulse width increases.
Eats the tomb load value through test 煴 Ju Di to twine the acute hearing to gather together the load for 8Ω the time maximum output not distorted sine wave ridge peak value is 8.4V (i.e. 4.2×2), the output is time the 1.1W,16MHz supply current is 278mA, the efficiency is 80%. But when 32MHz, the AD equivalent precision will enhance, the acoustic fidelity will be better, but the system static state power loss electric current will increase, however, because this loss basic fixed, will therefore design the digital power amplifier with Atmega8 to be more suitable to compare the high efficiency the situation use. In addition, enlarges between the IRF7389 source the voltage to be possible to increase outputs the PWM level, thus increases the output, further raises the efficiency.
4 concluding remark
Selects the Atmega8 monolithic integrated circuit design power amplifier to be simple, moreover the flexibility is good, extendibility, may also meet the different need through the tune-up procedure. Then changes the power amplifier frequency sound through the revision digital filtering procedure, if adds a piece of memory again, then realizes the sound recording, to retake courses, the hypothesis broadcast time and the demonstration volume and so on. But these functions through integrate D kind of power amplifier to be unable merely to complete.
