Abstract: SoC is the ultra large scale integrated circuit’s trend of development and the new century integrated circuit’s mainstream. Its complexity as well as cost fast requests and so on completes the design, to reduce, had decided system-on-a-chip’s design must use IP (Intellectual Property) the multiplying method. This article introduced that by may the multiplying IP design method, design serial peripheral device connection SPI (Serial Peripheral Interface) the module IP nucleus mentality, realize with the Verilog language, and after the FPGA confirmation, through TSMC (Taiwan integrated circuit manufacture company) 0.25μm the craft production line running water realizes, completes the anticipated function.
Key word: SoC may multiplying IP SPI the AMBA main line
Introduction
Along with the integrated circuit design technique and the deep submicron technique of manufacture’s swift development, integrated circuit’s scale was getting bigger and bigger, presented on the piece system SoC (System on Chip, also called it system-on-a-chip). As a result of it in the speed, the power loss and the cost aspect’s superiority, the development momentum is swift and violent. The SoC chip is a complex system, to complete the design in the scheduled time, and enhances the design the reliability, only then relies on based on IP the multiplying SoC design method. How is the SoC design provides may the multiplying IP nucleus, becomes the SoC design the foundation and the difficulty.
The Southeast University ASIC systems engineering engineering research center in view of AMBA (Advanced Microcontroller Bus Architecutre, advanced micro controller) the main line standard has developed a section of code number is the Garfield embedded microprocessor. This microprocessor besides uses ARM Corporation ARM7TDMI essence hard IP, other modules have used soft IP which one develop. This article take serial peripheral device connection SPI as an example, introduces based on the multiplying IP design and confirmation some experiences. This SPI module based on AMBA APB (Advanced Peripheral Bus, advanced peripheral device main line) the standard, may not make the revision application in any mark AMBA main line standard microprocessor design.
The Garfield overall construction and the SPI module position as shown in Figure which locates in the system 1.
1 may multiplying IP the nucleus SoC design method
In system-on-a-chip design, IP referring in particular to after confirmation each kind of super great unit modular circuit. VSIA (hypothesized component connection alliance) acts according to the design level, the IP division is three levels: Hard IP, soft IP and are situated between both’s solid IP. The hard IP performance is most superior, but the compatibility is bad, the soft IP flexibility is big, the probability is good. The IP nucleus must have the following characteristic:①Readability;②The design spreads out the malleability and the craft compatibility;③Measurability;④Port definition standardization;⑤Version board protection.
The code compilation rule and may synthesize the written standard realizes the IP nucleus foundation, may guarantee the IP soft nucleus under any EDA tool the translation and the synthesis accuracy. For the SoC integration when eliminates risk which the synthesis produces, we have formulated the Verilog code written standard, and requests to have the detailed annotation, easy other people understanding and revision. But multiplying IP design cycle as shown in Figure 2.
To integrate easily IP in the chip, needs to standardize on the connection or the piece the main line, VSIA has done certain work in this aspect. Moreover, in the design must dispense the IP tongue and groove joint oral area the function part to separate as far as possible, takes a module to carry on the design alone, when needs to integrate in other interconnection agreement, only need revise the connection part. For provides the flexibility as far as possible, when the permission synthesis establishes many parameters.
In faces the user finally in the product issue, the user’s manual is the very important part. This part of documents will use in the IP nucleus the choice, the integration and the confirmation, is one kind of unusual specialization Wen Lou. It mainly includes the module system structure, the function diagram, the input, the input/outlet, the succession chart, the transfer way, the design cycle, the test instruction, the recommendation use and the software compiler and the driver, the system confirmation instruction, the debugging instruction and this IP nuclear edition history and so on. In may entrust with heavy responsibility in the IP nuclear product issue, but should also contain this IP nucleus many kinds of simulation model, so that user when carries on the appraisal, the design and the system test uses. The IP nucleus’s simulator model may divide into 3 levels generally:①The behavior level model, can the simulation this IP nucleus complete function, including on the algorithm level and the set of instructions function;②The hardware level model, can provide this IP nucleus precisely the function and the succession simulation;③The gate level model, provides the hard core to have the succession counter-labelling information simulation model.
In reality, we search a set based on CVS (cooperation edition management system management system) the edition management and the design, confirm the personnel joint operation the formulation flow, has made as far as possible the comprehensive simulation to the RTL code, provides the complete test vector, had guaranteed finally the IP nucleus’s quality, and has established the standard, the standard documents according to the request.
2 SPI module IP nucleus design
Serial auxiliary equipment connection SPI (Serial Peripheral Interface) the bussing technique is many kinds of microprocessors which, the micro controller as well as the peripheral device one kind of full-duplex, synchronized, the serial data interface standard Motorola Corporation promotes. The SPI main line quantity plants three main lines, because its hardware function is very strong, therefore, is quite simple with the SPI related software, enables CPU to have more time to handle other business.
2.1 SPI module connection signal and succession request
(1) interior bus interface
The AMBA standard is on the piece which formulates by ARM Corporation the main line standard, was the SoC design has provided the following merit: Good may transplant and may the multiplying design, the low power loss design, ridicule lives can the system design which may transplant with the structure as well as the good measurable design. SPI is APB on main line’s Slave module. The APB main line succession is quite simple, has the interest reader to be possible to consult ARM Corporation “AMBA Specificetion” (Rev 2.0). Therefore this SPI module supports 3 kind of DMA operations, therefore besides the standard APB holding wire, but also some 3 and DMA module connection request holding wire.
Figure 3 and Figure 4
(2) SPI bus interface and succession
SPI main line including 1 serial synchronized clock holding wire as well as 2 data lines.
The SPI module to carry on the data exchange with the peripheral device, according to the peripheral device work requirement, its output serial synchronized clock polarity and the phase may carry on the disposition, the clock polarity (CPOL) to the transport protocols not significant influence. If CPOL=0, the serial synchronized clock’s idling condition is the low level; If CPOL=1, the serial synchronized clock’s idling condition is the high level. The clock phase (CPHA) can dispose uses in choosing one of two kind of different transport protocolses to carry on the data transmission. If CPHA=0, in the serial synchronized clock’s first jump along (rise or drop) data by sampling; If CPHA=1, in the serial synchronized clock’s second jump along (rise or drop) data by sampling. The SPI main module and should be consistent with it correspondence’s peripheral device sound clock phase and the polarity. SPI connection succession like chart 3, shown in Figure 4.
2.2 SPI module functional design
According to the function definition and the SPI principle of work, divides into entire IP 8 submodules: APB interface module, clock frequency division module, transmission data FIFO module, receive data FIFO module, state machine module, transmission data logic module, receive data logic module as well as interrupt form module.
Analyzes SPI four kind of transport protocols to be possible thoroughly to discover, according to one kind of agreement, so long as carries on the transformation to the serial synchronized clock, can obtain other three kind of agreements. In order to simplify the design stipulation, if wants serial transmission many data, inserts a serial clock’s idle waiting between two data transmissions, such state machine only needs two conditions (free time and work) can work correctly. Compares other designs, in basic does not reduce the performance under the premise, mentality comparison fining, clear.
This SPI module has two workings: Inquiry way and DMA way. The inquiry way monitors the condition which through the processor nucleus SPI the condition register attains its locates, thus decision next step movement. DMA way by DMA modular control data in memory and SPI exchange, but does not need the processor nucleus the reference, raised the main line use factor effectively.
3 EMA software simulation and FPGA confirmation
In order to guarantee that the design robustness, the utilization many kinds of method IP function carries on the comprehensive simulation and the confirmation regarding this.
First carries on the EDA software simulation confirmation. This kind of simulation including the RTL level and gate level simulation confirmation. The RTL level simulation is only calls in the code file the hardware description language the simulation software to carry on the function simulation, the inspection logical function to be whether correct. Gate level simulation after layout wiring and layout wiring simulation. After layout wiring the simulation, may obtain the quite precise latency parameter, can reflect quite really after the chip manufacture completes, module in practical work behavior and performance, therefore adopted this kind of simulation to think that the module designed successfully, might carry on the class piece. RTL level code conversion Cheng Menji net table, what uses is Synopsys Corporation’s comprehensive tool DC (Design Compiler) as well as Taiwan integrated circuit manufacture company (TSMC) 0.25μm standard cell storehouse.
Carries on the function confirmation in the traditional design cycle, first needs through to write the test vector the way for to need to carry on the function testing the module to add the drive, then through observation module output result, judgment module function to be whether correct. But when writes the test vector, tests engineer is in oneself understood to the module function in the foundation carries on. This has a problem, the test vector has the possibility to the module drive is incomplete, but also has the possibility is wrong, but the test vector’s drive has not caused to manifest wrongly; Also has the possibility module function is correct, reported mistakenly that causes the difficult card process becomes wrongly the unusual low efficiency. In order to avoid the above question, in the module function confirmation, uses the system-level confirmation environment. This environment by IP the main line, the driver, the monitoring device, the external module and is coordinated the script which they work to be composed. Composition system’s various modules may demand must join the environment. Each time the proof procedure is the corresponding drive function in the environment process. The confirmation result has, the examination and the output by the environment. This confirmation environment under the SOLARIS5.8 operating system, the simulator uses Synopsys Corporation’s VCS, supports C/C , Verilog and the VHDL coordination simulation, may the direct SPI module hang in the confirmation environment, through the Verilog $readmemh duty read-in software drove that carries on the confirmation.
In the system clock is under 66MHz, CPOL=1, CPHA=0 receives and dispatches 6 byte data simulation result like chart 5, 6 to show.
Figure 6
The SPI module’s model application is: Through and has the SPI connection touchscreen control chip connection, provides to the touchscreen the support. In view of this goal, loads the SPI module and other essential modules to FPGA in carries on the hardware, the software union debugging, carries on the confirmation to the actual electric circuit. We have selected the most common four type resistance type touchscreen, but the touchscreen control chip uses ADS7843. ADS7843 is a built-in 12 a/d conversion, the low breakover resistance analog switch’s serial interface chip, supports 8 and 12 A/D conversion accuracy. In order to complete a time electrode voltage cut and A/D transforms, the microprocessor needs first through the SPI connection toward the ADS7843 transmission control word, after the transformation completes, again through the SPI connection read-out voltage transformation value. A standard transformation needs 24 clock cycles. Typical application electric circuit as shown in Figure 7.
SPI FPGA confirms the platform Intergrator/LM-EP20K1000E which and the Intergrator/CM7TDMI development confirmation board as well as the Garfield II confirmation circuit wafer provides including ARM Corporation (voluntarily design). And on the Intergrator/CM7TDMI ARM7TDMI microprocessor essence takes entire development system’s CPU. Through ARM Multi-ICE, will confirm essential loads including SPI all modules from the JTAG mouth to the Intergrator/LM-EP20K1000E board on Altera APEX20K series EP20K1000EFC672. The peripheral circuit (contains ADS7843) by the Garfield II confirmation circuit wafer as well as the touchscreen is composed. On FPGA through the software and hardware coordination confirmation, observes the SPI main line signal through the logical analyzer, also proved that this SPI module performance is good.
Figure 7
Moreover, through Taiwan integrated circuit manufacture company (TSMC), uses its 0.25μm standard cell storehouse to carry on the running water confirmation many times to this design, obtains the actual IP electric circuit works in the prototype very stably. Hence, the IP design is very successful. When designs the similar construction the SoC chip, may after needs to dispose the corresponding parameter carry on the multiplying directly.
Conclusion
The establishment undergoes the full confirmation the function to be correct, the performance good may the multiplying IP module storehouse, is carries on the SoC design fast the foundation and the request. The design may multiplying IP, need to observe certain design method: Complete, clear documents; Good code style; Detailed annotation; Careful design verification environment; Extremely high code coverage fraction test vector and so on. This article take SPI module IP as an example, according to the standard flow and the request, has carried on the preliminary attempt, obtained the good result.
