Abstract: This article mainly discussed has used the EDA tool to design the Chinese character trundle monitor’s technical question. In the article first described based on the scene programmable gate array (FPGA) hardware circuit; Then studied on 8×8LED the light emitter diode lattice had demonstrated that the trundle Chinese character the principle, and gave described its function VHDL language programming based on ALTERA parametrization model base LPM; Finally for uses the EDA tool software processing to demonstrate that the data file the method has carried on the discussion.
Key word: The hypothesized component VHDL language and applies the EDA technology
Uses the conventional routes design the Chinese character trundle monitor, usually needs to use the monolithic integrated circuit, the memory and the restriction logic circuit carries on PCB (print circuit wafer) the board level system integration. Although this kind of plan has the monolithic integrated circuit software’s support to be more flexible, but as a result of hardware source’s limit, in the future to the design change and the promotion, with difficulty will always avoid being probable to pay the many research and development funds and the long delivery market cycle price.
Along with the electronic design automation (EDA) the technical progress, is valued people’s more and more based on the programmable ASIC component’s digital electron system design’s complete plan, and take the EDA technology as core, can carry on the system chip integration on the programmable ASIC component the new design method, is also substituting fast based on the PCB board traditional design way.
How uses the EDA tool to design the electronic system is the people universal issue of concern. In EDA tool software MAX PLUSⅡUnder the support, this design adopted the translation, adaptive and the software simulation confirmation. Finally used to write down the real experiment system’s hardware experiment to prove its accuracy.
Hardware design
In order to simplify the discussion, this article only studies on the single 8×8 LED light emitter diode lattice rolls demonstrates the multi-Chinese character information the question.
Figure 1 gives is uses American ALTERA Corporation 10K the series FPGA design to be possible to support the trundle to demonstrate the multi-Chinese character information the general hardware circuit.
In the chart, the standard JTAG connection and PC machine and the mouth are connected, use in downloading the design feature to FPGA in; LED lattice data line after FPGA I/O line string 300Ω limiting resistor actuates, but the sw line actuates directly by the FPGA I/O line. The LED lattice uses the scanning type working, controls the sw line the scan round signal to be effective for the low level, demonstrated that data data is the high level is effective.
Because the ALTERA 10K10LC84-4 chip interior has the enough RAM resources, therefore this design has not used exterior RAM.
Moreover, in chart disposition EPROM is may choose, only then, when request Chinese character trundle monitor off-line movement only then needs to use.
The trundle demonstrates the multi-Chinese character information the principle
For demonstrates the Chinese character on 8×8 the LED light emitter diode lattice, must first express into the Chinese character as shown in Figure 2 8×8 picture element chart.
In Figure 2, data0~data7 respectively be presses the Chinese character picture element information which a row extraction arranges in order, has 8 word lengths.
Then, in turn to the multi-Chinese character extraction picture element information, and sequential queue depositing in ROM, then may obtain one to treat the demonstration data series. Further controls this data series through the addressing method the release process, may realize on 8×8 the LED light emitter diode lattice rolls demonstrates the multi-Chinese character information the goal. Figure 3 gives is realizes the trundle to demonstrate the multi-Chinese character information the principle schematic drawing.
May know by Figure 3, one time can in demonstrate in the data series to locate treats the demonstration data the address pointer available equation below computation:
addr=n m (1)
Obviously, the n value scope should be 0~N, and controls the Chinese character demonstration by it the spin rate; the m value scope should be 0~7, and decides LED by it the lattice the row switch sw scanning velocity. Therefore, controls n to sweep treats the demonstration data completely the time, may adjust the Chinese character information the spin rate; Changes m the repeated sweep cycle, may improve on the LED lattice demonstrates the complete Chinese character information the stability.
In addition must point out that because type (1) operation must depend on the hardware to realize, therefore the address pointer addr mold should take is N, moreover to realize the complete Chinese character information to roll the LED lattice, must supplement 8 spatial data bytes before data N.
Display principle which gives according to Figure 3, we may construct the hardware which it corresponds to realize structure as shown in Figure 4.
Principle which shows according to Figure 4, we designed described FPGA the essence hardware function VHDL language procedure. This design has used ALTERA Corporation’s MAX PLUSⅡ In the PLD research and development tool’s parametrization model base, and has adopted the structurized description way.
Below is the VHDL procedure which we design:
Demonstrates the data file the Canada side law
In the VHDL design, the ROM unit’s initialization data must provide by demonstration data file data.hex, moreover this document’s data depositing must conform to Intel the HEX form. Because from the Chinese character direct extraction’s demonstration data is the binary code, therefore cannot use in producing the data.hex document directly, therefore needs to draw support from other EDA tool to help to process the data.hex document. Below gives processing demonstration data file data.hex the concrete step:
1st, to the multi-Chinese character extraction picture element information, forms arranges according to sequence treats the demonstration data series;
2nd, uses Heluo Corporation’s multi-purpose programmer ALL03 or all07 application software, will treat demonstration data smoothing into BIN the form binary system data file data.bin;
3rd, uses ten thousand advantage company’s monolithic integrated circuit simulator software, transforms into Intel HEX binary system data file data.bin the form demonstration data file data.hex.
Certainly, we may also use the monolithic integrated circuit simulator’s application software to come direct processing demonstration data file data.hex, but this need to has the binary code demonstration data to carry on the software programming, therefore was inferior that the above method is succinct.
Experimental verification
In order to confirm the design the accuracy, we use EDA tool software MAX PLUSⅡThe simulation simulator, to carried on the analog simulation confirmation through the translation Chinese character trundle monitor’s VHDL design, the experiment had proven that the Chinese character trundle and the reading scan situation was normal, i.e. the FPGA essence hardware work was good, might realize the design function correctly.
In addition, the Chinese character trundle monitor’s VHDL soft nucleus design has also been written down basis chart 1 in the construction real hardware system. Has also obtained the result which to hardware system’s experimental verification tallies with the software simulation simulation conclusion.
Therefore, we may draw following conclusion:
1st, the EDA technology not can only reduce the digital electron system design the complexity and the difficulty, moreover can also obviously strengthen the design the flexibility;
2nd, many kinds of EDA tool’s union application, is helpful to enhancement rated capacity and the reduction design cycle;
3rd, gains the software simulation simulation result using the EDA tool to have the same traditional hardware empirical datum same importance and the confidence level.
