Abstract: In has analyzed the DDS basic principle as well as in the AD9858 essential feature foundation, introduced AD9858 delivers the number way and the monolithic integrated circuit interface routine. Gave has realized the frequency-hopping time using the AD9858 interior register is smaller than the 50ns 4 frequency fast-frequency hopping’s concrete method.
Key word: DDS; AD9858; Fast-frequency hopping
In the electronic system, needs the application frequency synthesis technology to realize the frequency-hopping source design frequently. The frequency synthesis refers to a high stable reference frequency carries on each kind of technical processing, produces a series of stable frequency output. At present what applies is broadest is the phase-locked loop (PLL) the frequency synthesis technology, it is through changes in PLL the frequency division to realize the frequency-hopping compared to N, but between the PLL avoidless ring circuit locking time reduction and the frequency resolution enhancement and the stray reduce the contradiction, therefore very difficult simultaneously to satisfy the high speed frequency-hopping and the thin length of stride, the low stray request. The direct digital frequency synthesis (DDS) is one kind of new frequency synthesis technology. It has the frequency resolution to be high, the frequency cuts, when quickly the frequency cut phase continual and so on merits, thus is widely applied in systems and so on radar frequency-hopping, correspondence, electronic countermeasure.
1 DDS basic principle
DDS functional block diagram as shown in Figure 1. The phase accumulator under A frequency control word FCW control, take reference clock frequency fc as the sampling rate produces treats the composite signal phase the digital linear sequence, then takes its Gao PWEI the address, produces S correspondence waveform digital sequence S(n) through inquiry sine table ROM, transforms again by the d/a converter it as the steps and ladders analogue voltage profile, finally outputs smoothly by low pass filter LPF for the sine wave.
Frequency control word FCW and clock rate fc has decided DDS output signal frequency fo together. Its relations are:
Output frequency: f0=FCW fc/2A
The frequency resolution is: the fo=fc/2A 2 AD9858 characteristics and deliver the number way
AD9858 main feature:
* has 1,000,000,000,000,000 time/second sampling speeds;
* has reaches as high as 2GHz the input clock (to adopt 2 frequency divisions);
* the integration has 10 D/A switches;
* contains 32 programmable frequency registers;
* has 8 bit parallel and the SPI serial control interface;
* has the automatic frequency scanning function;
* inner tube 4 frequency registers;
* uses the 3.3V low power source power supply;
* the electric charge pump independent power line voltage may reach 5V;
* the integration has the 2GHz mixer.
Because DDS produces the frequency is by the frequency control word FCW control, the change corresponding frequency’s control word then obtains needs the frequency. Therefore DDS delivers the number method realizes one of DDS frequency-hopping source keys. Its internal structure diagram as shown in Figure 2.
AD9858 has parallel and the serial two kinds delivers the number way. The data transmits from the user to the DDS component core needs two steps. When writes the operation, no matter with parallel delivers the number way serial to deliver the number way, the users must first read in the data the I/O buffer. When the data locks into the storage register from the I/O buffer, the DDS core only then receives the data. In AD9858, triggers the FUD foot or changes the pre-programming Profile to be possible to cause in the I/O buffer’s data to enter DDS the core storage register.
when (1) parallel delivers the digital-analog type, the system should activate eight bidirectional data mouths (D0~D7), six address input ports (ADDR5~ADDR0), to read the mouth (RD) and writes the mouth (WR), register’s choice the address decision which provides by the register chart. Read-write function by RD and WR pulse triggering control, but these two functions cannot also have an effect. The read-write data may through the D0~D7 foot transmission.
Figure 2
(2) serial delivers the digital-analog type including two stages. The first stage constitutes by a 8 instruction cycle. The highest order is a flag bit, uses in determining that is reads the operation or writes the operation, low six are serial delivers the number goal register’s address. The second stage is delivers the data to the register.
Many time DDS requests the fast-frequency hopping, but the frequency fast change requests register’s frequency control word to renew fast, therefore, usually requests DDS to select parallel delivers the number. Is opposite chip says 煟 grain of mold stem luck load Fu Naopan in ADI Corporation former DDS the garden plan to pay respects to has four frequency registers and four phase compensation register 熣 delicacy ditch pledge may facilitate the fast production frequency-hopping signal as well as the four-phase code coded modulation signal 煻, and its switching time is extremely short. This is because frequency-hopping’s frequency control word already sent in the DDS core register’s four group of control register, the frequency between choice depends upon external selection signal PS1 and PS0 realizes.
3 design based on the AD9858 fast-frequency hopping
3.1 frequency-hopping electric circuits
Delivers the number and four frequency cut completes through the monolithic integrated circuit. the 89C51 monolithic integrated circuit may work under the 5V voltage, but tests proved that when 3.3V power supply, the 89C51 monolithic integrated circuit’s work is also completely normal, uses the monolithic integrated circuit and DDS chip AD9858 design frequency-hopping schematic diagram like chart 3.
3.2 software routine design
According to the AD9858 succession characteristic, may separately is connected monolithic integrated circuit’s P1.0 and P1.1 with RD and WR. Thus, when programming may makes the following concrete establishment to the frequency control word and the phase compensation character address tabulation:
FTW0_1 EQU 00101011B
FTW0_2 EQU 00101111B
FTW0_3 EQU 00110011B
FTW0_4 EQU 00110111B
POW0_1 EQU 00111011B
POW0_2 EQU 00111111B
Lowest two respectively are RD and WR, when the initialization sets at it for the top digit. Three to six delivers the number the address. Frequency delivers the number procedure to be as follows:
MOV P3, 40H
MOV P1, #FTW0_1
CLR WR_
SETB WR_
SETB FUD
CLR FUD
MOV P3, 40H
MOV P1, #FTW0_2
CLR WR_
SETB WR_
SETB FUD
CLR FUD
MOV P3,40H
MOV P1, #FTW0_3
CLR WR_
SETB WR_
SETB FUD
CLR FUD
MOV P3, #40H
MOV P1, #FTW0_4
CLR WR_
SETB WR_
SETB FUD
CLR FUD
;
MOV P3, #00H
MOV P1, #POW0_1
CLR WR_
SETB WR_
SETB FUD
CLR FUD
;
MOV P3, #00H
MOV P1, #POW0_2
CLR WR_
SETB WR_
SETB FUD
CLR FUD
When design, should send in first 8 frequency control words monolithic integrated circuit’s P3 mouth, then sends in these 8 addresses the P1 mouth. Because delivers 8 bit addresses at the same time also to set WR for the top digit. Therefore, sets at WR accepts a lower status may sends in 8 control words and 6 bit addresses the DDS buffer. Because the frequency renewal only needs a FUD rise along, therefore sets at FUD for the top digit may the frequency register which sends in 8 bit data assigns (initialization set FUD for low position), finally sets at again FUD for the low position, thought that behind the frequency renewal establishment rise along prepares.
May send in through a simple procedure a frequency control word DDS the storage register. Again and delivers the number way through the same address tabulation to be possible other three frequency spot which needs to send in DDS the storage register. Thus, may carry on the cut fast through external selection signal PS1 and PS0 in these four frequency.
Because the AD9858 internal frequency register is limited, therefore, when frequency-hopping’s frequency are many, each time the frequency-hopping needs to change the frequency control word. The DDS actual frequency-hopping time including delivers the number and the internal switching time. If uses the internal register controls the switch frequence through PS1 and PS0, then frequency-hopping time only then interior switching time, therefore, this kind of frequency-hopping is quite quick.
Figure 3
4 experiments and test result
The experiment indicated that (this experiment uses 400MHz to lower chirp clock): The AD9858 internal switching time is only a nanosecond level. This experiment uses the cycle logic level to control PS1 and PS0, and through realizes the frequency cut to PS1 and the PS0 signal’s choice. Finally the use ondograph tests the frequency-hopping time.
The author carries on the first experiment is selects a register’s frequency FCW to suppose is 00000000H (0MHz), another register’s frequency selects FCW to suppose is 20000000H (125MHz). The test result is: From the 0MHz frequency-hopping the time which uses to 125MHz is 17.6ns.
The second experiment is selects a register’s frequency FCW to suppose is 19999999H (100MHz), another register’s frequency selects FCW to suppose is 20000000H (125MHz). The test result is: From the 100MHz frequency-hopping the time which uses to 125MHz is 33.6ns.
5 conclusions
From the result which two times tests looked that realizes the fast-frequency hopping using the AD9858 interior register is completely feasible. Because in the test procedure has the data transmission to retard, PS0 and PS1 control level rise along, therefore test existence certain error, the actual frequency-hopping time should be shorter than the test result some.
Because the AD9858 interior has four frequency registers, therefore frequency-hopping’s spot is limited. Does not need, the frequency-hopping time request many in frequency-hopping very short-time, this method superiority is very obvious.
