Abstract Take the GMS97C2051 monolithic integrated circuit as the core, uses TLC2543 12 serial bit A/D switch, has designed a serial data gathering/transmission module, has given the hardware schematic diagram and the main source program.
Key word Serial A/D switch Serial data transmission GMS97C2051 monolithic integrated circuit
In the microcomputer observation system, must use A/D frequently to transform. The commonly used method is the expansion together or many A/D gathering card. When the simulation quantity are few perhaps the temperature, the pressure and so on slow changes the signal situation, uses always the linear A/D card is not most appropriate, the most economical plan. Here introduced that one kind take the GNS97C2051 monolithic integrated circuit as a core, uses sampling module which TLC2543 12 serial bit A/D switch constitutes, this module sampled data by monolithic integrated circuit serial port after level switch delivers the superior machine (IBM the PC compatible machine) serial port COM1 or COM2, form one kind of serial data gathering serial data transmission the way. Confirmed after the practice debugging: This module dissipation is low, the sampling precision is high, the reliability is good, the connection is simple, has the certainly use value.
1 main component introduction
1.1 TLC2543 serial A/D switch
The module uses TI Corporation’s TLC2543 12 serial bit A/D switch, uses the switch electric capacity to approach the technology to complete a/D switching process gradually. Because is the serial input structure, can save 51 series monolithic integrated circuit I/O resources, and moderate cost. Its characteristic includes:
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TLC2543 pin arrangement as shown in Figure 1. Figure 1 AIN0~AIN10 is simulates the input end;
In order to select patches or strips of land as worth saving for seed the end; DIN is the serial data input end; DOUT is a/D transformation result three states of matter serial out-port; EOC was the transformation conclusion end; CLK is the I/O clock; REF is the datum voltage terminal; REF- is negative datum voltage terminal; VCC is a power source; GND is the place.
1.2 GMS97C2051 monolithic integrated circuits
GMS97C2051 is one performance price which the Wuhan Strength Source Company and South Korean LG Corporation promotes jointly compared to the extremely high 8 monolithic integrated circuits, its command system and the MCS-51 series is completely compatible. GMS97C2051 and AT89C2051 compatible (may direct replace), but its performance price ratio surpasses AT89C2051. Pin arrangement as shown in Figure 2.
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1.3 level switch MAX3232
MAX3232 is the RS-232 transceiver, simple easy to use, the list 5V power source power supply, only needs external connection several electric capacities then to complete from the TTL level to the RS-232 level transformation, pin arrangement as shown in Figure 3.
2 hardware designs
Hardware circuit as shown in Figure 4. |
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Monolithic integrated circuit GMS97C2051 is overall system’s core, TLC2543 carries on gathering to the input simulated signal, the transformation result (9 feet) receives by the monolithic integrated circuit through P3.5, the AD chip’s port select and the way data (8 feet) input through P3.4 to an its internal 8 bit address and the control register, the monolithic integrated circuit gathering data through the serial port (3, 2 feet) transform the RS232 level after MAX3232 to the superior machine transmission. In the chart the serial LCD display circuit only uses in debugging, to gathers/the transmission data to carry on the monitor.
3 monolithic integrated circuit software design
The monolithic integrated circuit procedure mainly includes the serial data gathering module “DATA_SAM” and the serial data transmission module “RS232″, debugs the demonstration subroutine which uses in this to leave out.
The TLC2543 port select and the way data are 8, its function is: D7, D6, D5 and D4 use for the channel which chooses the request to transform, when D7D6D5D4=0000 chooses 0 channels, when D7D6D5D4=0001 chooses 1 channel, analogizes in turn; D3 and D2 use for to choose the output data length, this program selection output data length is 12, namely D3D2=00 or D3D2=10; Before the D1, D0 selection input data leads the position, before the D1D0=00 choice top digit leads.
TLC2543 in each time the I/O cycle read’s data is the previous transformation result, current transformation result in the next I/O cycle by serial emigration. The first reading as a result of internal adjustment, read transformation result possible inaccurate, should discard.
The data acquisition procedure is as follows:
| DATA_SAM: | ||
| MOV R0,#30H |
; Data buffer first address 30H→R0 |
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| MOV R1,#00000000B | ; 0 channel way/channel data | |
| ACALL RD_AD | ; First time reads transformation result possible inaccurate, discarding. | |
| MOV R1,#00010000B | ; 1 channel way/channel data | |
| ACALL RD_AD | ; Delivers 1 channel way/channel data and reads the 0th channel switching result | |
| MOV @R0, R2 | ; The transformation result deposits to the data buffer, similarly hereinafter | |
| INC R0 | ||
| MOV @R0, R3 | ||
| INC R0 | ||
| MOV R1,#00100000B | ; 2 channel way/channel data | |
| ACALL RD_AD | ; Delivers 2 channel way/channel data and reads the 1st channel switching result | |
| MOV @R0, R2 | ||
| INC R0 | ||
| MOV @RO, R3 | ||
| INC R0 | ||
| ………… | ; Other channel operating mode analogy | |
| RET | ||
The monolithic integrated circuit produces the serial clock through the programming, and according to the succession transmission and the receive data position, completes the channel way/channel data read-in with the transformation result read-out, the procedure is as follows, for data acquisition module “DATA_SAM” transfer.
| CLK EQU P3.3 | ||
| DIN EQU P3.4 | ||
| DOUT EQU P3.5 | ||
| CS EQU P3.7 | ||
| RD_AD: | ||
| CLR CLK | ; Clear I/O clock | |
| SETB CS | ; The establishment select patches or strips of land as worth saving for seed high to | |
| CLR CS | ; The establishment select patches or strips of land as worth saving for seed lowly to | |
| MOV R4,#08 | ; Reads high 8 first | |
| MOV A, R1 | ; Puts The way/channel control word | |
| LOP1: | ||
| MOV C, DOUT | ; Reads the transformation result | |
| RLC A | ; A register shifts to the left, moves in the result data position, the emigration way/channel control position | |
| MOV DIN, C | ; Output mode/channel position | |
| SETB CLK | ; Establish the I/O clock high to | |
| CLR CLK | ; Clear I/O clock | |
| DJNZ R4, LOP1 | ; R4 is not 0, then returns to LOP1 | |
| MOV R2, A | ; Transformation result’s high 8 put to R2 in | |
| MOV A,#00H | ; Repositions a register | |
| MOV R4,#04 | ; Reads low 4 again | |
| LOP2: | ||
| MOV C, DOUT | ; Reads the transformation result | |
| RLC A | ; A register shifts to the left, moves in the result data position | |
| SETB CLK | ; Establish the I/O clock high to | |
| CLR CLK | ; Clear I/O clock | |
| DJNZ R4, LOP2 | ; R4 is not 0, then returns to LOP2 | |
| MOV R3, A | ; Transformation result’s low 4 put to R3 in | |
| SETB CS | ; The establishment select patches or strips of land as worth saving for seed high to | |
| RET | ||
The serial data transmission module including the serial port initialization subroutine and the data transmission subroutine, various subroutines distinction is as follows. And the data transmission selects the inquiry method, may also change the interrupt mode conveniently.
| INIT_COM: | ||
| MOV SCON,#50H | ; Serial port way 1 work, 8 bit data positions, 1 stop position, non-parity check | |
| MOV PCON,#80H | ; SMOD=1, the baudrate increases time | |
| MOV TMOD,#20H | ; Baudrate establishment, fOSC=12MHz, baudrate =2* 2400, N=0F3H | |
| MOV TH1,#0F3H | ||
| MOV TL1,#0F3H | ||
| SETB TR1 | ; Start timer T1 | |
| RET | ||
| RS232: | ||
| MOV R0,#30H | ; Buffer first address 30H→R0 | |
| MOV R5,#22 | ; Transmission data length →R5,11* 2=22 | |
| LOOP: | ||
| MOV A,@R0 | ; Takes the data →A | |
| MOV SBUF, A | ; Data →SBUF | |
| WAIT: | ||
| JBC TI, CONT | ; The judgment transmission interrupt symbol, is 1 piece changes to CONT, and clear TI | |
| SJMP WAIT | ||
| CONT: | ||
| INC R0 | ||
| DJNZ R5, LOOP | ||
| RET | ||
4 superior machine serial port receive programming
The superior machine receive data uses the C language procedure including the initialization subroutine and the receive subroutine. Various subroutines distinction is as follows:
| void init_com1(void)/* initialization subroutine */ | |
| { | |
| outportb(0×3fb,0×80); the/* line control register high position 1, causes baudrate establishment effective */ | |
| outportb(0×3f8,0×18); the/* baudrate establishment, with the monolithic integrated circuit baudrate is 4800bps*/identically | |
| outportb(0×3f9,0×00); | |
| outportb(0×3fb,0×03); /* line control register establishment, 8 bit data positions, 1 stop position, non-parity check */ | |
| outportb(0×3fc,0×03); the/*Modem control register establishment, causes DTR and RTS outputs effective */ | |
| outportb(0×3f9,0×00); the/* establishment interrupt permission register, forbids to interrupt */ | |
| } | |
| void receive_data(void)/* inquiry way receive data subroutine */ | |
| { | |
| while (! kbhit()) | |
| { | |
| while (! (inportb(0×3fd)&0×01)); if/* receive the register to spatially, then waits for */ | |
| printf (”%x”, inportb(0×3f8)); the/* read result and demonstrates */ | |
| } | |
| getch(); | |
| } | |
5 conclusions
This article gives hardware and software after practice examination, and already deferred to the PC/104 main line to manufacture the data acquisition card, the use is very convenient, can satisfy to the data sampling frequency request is not the specially high application situation.
