The abstract through to TI Corporation TMS320C5000 series DSP the HPI main line and the PC104 main line succession’s analysis, take the VHDL language as a tool, uses Altera FPGA chip EP1K50, the design completes the PCI04 main line and DSP between the HPI main line’s correspondence connection, and in one section take TMS320VC5409DSP as the data acquisition processor, grinds the Chinese embedded labor to control motherboard PCM-5825 is embedded data acquisition system Shanghai which the system board composed obtained the utilization; Gives confirms the connection design with the entire connection design related VHDL source code and on PCM-5825 the X86 assembly language procedure.
Key word DSP HPI PC104 main line FPGA VHDL source code
In a section of embedded data acquisition system’s design, uses TMS320VC5409 DSP to take to multi-channel signal gathering and the pretreatment, after the processing data delivers to 12.7 Cm(5in) labor controls in the computer to carry on the analysis and the preservation. Because the labor controls machine the main line is PC104, therefore needs to design between PC104 and the DSP correspondence connection. In the system comes by Altera Corporation’s piece of FPGA chip EPlK50 to this connection and in the data acquisition process logical control and FIFO carries on the design. Below mainly elaborates this correspondence connection design.
1 DSP HP0 connection
TMS320VC5409 DSP HPI is 8 parallel interfaces, mainly uses for with the main equipment or the main processor connection. The DSP interior has the certain amount double to visit RAM, may visit this RAM region besides DSP itself, the main engine may also realize through the HPI mouth visit to double visits RAM, thus realizes the main engine and the DSP correspondence.
The HPI connection through HPI control register HPIC, address register HPIA, data register HPID and so on 3 HPI registers carries on controls and realizes the data transmission. These 3 registers are 16, therefore the main engine visits time these registers needs to divide two operations to be able to complete.
HPIC only then 4 use in controlling HPI the operation, this 4 are located at the high byte and low byte low 4 separately, and stipulated that HPIC the height byte must be the same:
Bit 0 /8 (BOB) 11 use in the byte sequential control, BOB=1 expressed that the 1st byte is the low byte, otherwise the 1st byte is the high byte;
Bitl /9 (SMOD) 11 visit mode control, SMOD=l expresses sharing visit pattern (SAM), otherwise for main engine visit pattern (HOM);
Bit 2 /10 (DSPINT) 11 main engines through write this position l to come to transmit to DSP 1 HPI interrupt;
Bit 3 /11 (H1NT) 11 DSP through to this position l, causes exterior pin HINT to have a low electronic achievement to give main engine’s interrupt, the interrupt elimination must write l by the main engine to this position to eliminate.
HPID is the data register, the main engine realizes through read-write this register to shares RAM the read-write, the RAM address decided by the HPIA address register’s content. Therefore, the main engine visit to DSP the process is, reads in the address which first toward HPI address register HPIA wants to visit, then carries on again visit to data register HPID reads or writes.
The HPI connection signal includes:
The HAS 11 inputs, the address lock saves the signal, may connect the high level;
HBIL 11 inputs, byte identification signal, what uses for to distinguish the transmission is the high level or the low level;
HCNTL [1..0] 11 inputs, the HPI register’s visit address signal, the main engine uses for to choose the visit the HPI register. If table l arranges in order;
The HCS 11 inputs, HPI selects patches or strips of land as worth saving for seed the signal, the low level is effective;
HD [7..0] 11 bidirectional three states of matter data bus;
HDS1/HDS2YIYI the data feeds gating signal, may one meets the low level, another meets the logical control;
The HINT 11 outputs, for main engine’s signal of stop, position control by HPIC register’s HINT;
The HRDY 11 outputs, HPI prepares, the high electron is effective;
HR/the W 11 inputs, the read-write control signal, the high electron expressed that the main engine carries on reads the operation, the low electron expressed that the main engine carries on writes the operation.
HPI visit succession like chart l shows. As mentioned above, visits when the register needs to divide two operations to be able to complete.
2 PC104 main lines
The PC104 main line is grows from the ISA main line comes, is mainly to meet embedded system’s need. In 8.89 cm (3.5 in) and 12.7cm(5in) labor controls in the motherboard, mostly uses the PC104 main line to take the standard interface main line. The PC104 main line altogether has 104 pins, the overwhelming majority is completely consistent with the ISA main line signal characteristic, only then the extremely individual signal has the difference, therefore in the application definitely may according to the ISA main line use. The PC104 main line and the ISA main line are the same, is one 16 and 8 at the same time compatible main lines. In this system, what uses is 8 ways, takes PC104 the DSP HPI mouth main line’s 8 I/O equipment. PC104 main line’s I/O visit succession like chart 2 and shown in Figure 3.
According to PC104 main line’s I/O visit succession, only need use the following main line signal, then completes 8 main line’s correspondence designs:
SD [7..0] 11 PC104 data bus;
SA [9..0] 11 PC104 address bus;
IOW 11 PC104 ports write the control, the low level is effective, expressed that writes the operation to the I/0 mouth, by OUT instruction execute;
IOR a PC104 port reads the control, the low electron is effective, expressed that reads the operation to the I/O mouth, by IN instruction execute;
SYSCLK 11 PC104 main line clock;
The ALE 11 address locks save the signal, does not serve as the address lock in this to save, but serves as the bus cycle the start synchronization, its drop along expression bus cycle start;
IOCHRDY 11 I/0 device ready signal, when this level for low (invalid condition), indicated that the I/0 equipment must lengthen the bus cycle, the signal leads the way the gate actuation by the three states of matter gate or the collecting electrode;
IRQ 11 interrupt request signal, when the I/O equipment needed already prepared after the PC machine correspondence perhaps the gathering signal, initiated the interrupt to PC, the application correspondence, PC reads the data.
3 connection designs
According to the front analysis, obtains connection principle as shown in Figure 4.
In Figure 4, FPGA is EPlK50. The EPlK50 interior has 2880 logical units, 40 960 RAM. In this system, not only as HPI and PC104 interface logic, but also has other functions, like FIFO, A/D control and so on.
The EP1K50 essence power line voltage is 2.5 V, I/O power line voltage is 3.3 V, may direct and the I/O power line voltage also be 3.3 V TMS320VC5409 DSP is connected. Moreover, EPIK50 can withstand - the 0.7~5.75V input electron, loses the origin and the TTL level is compatible, therefore EP1K50 may also main line be directly connected with 5 VTTL the level PC104, thus the electrification flat turn trades in DSP and between the PC104 main line the function, cannot use other electronic communication component again, simplified the circuit design.
Regarding the connection design, most main is the succession design. The succession design has been correct, the system can work correctly. After synthesizing the HPI visit succession and the PC104 main line’s read-write succession, obtains the following design method:
①May realize regarding the HPI register’s visit through the address code, occasionally the address corresponds register’s low byte, the wonderful address corresponds register’s high byte, like Table 2 arrange in order.
Therefore the corresponding signal relations are:
HCNTL [1..0] =SA [2..1]
HBIL=SA[0]
When SA [9..0] =0×350~0×357, HCS=0, SA [9..0]
When for other values, HCS=1.
②HD [7. O] and SD [7..0] design the doubling to the main line.
③HR/W production: When PCI04 carries on reads the operation, HR/W=1; When PC104 carries on writes the operation, HR/W=0. Therefore:
HR/W=0, when IOR=1 and IOW=0;
HR/W=1, when IOR=0 and IOW=1.
④Meets the low electron in DSP General HDS2, HDSl when HBIL is directly 0 and HBIL is 1, separately has a change along, with selects the data. This signal’s production is the connection designs the successful key. Uses PCI04 in this main line’s system clock signal SYSCLK to count the production. The detailed process may see also the VHDL code.
⑤PCI04 main line’s interrupt request signal IRQ=HINT takes must. Because PC104 establishes as the rise along the interrupt.
⑥PC104 main line’s exterior I/0 prepares signal IORDY to meet HPI when the address strobe effective process the mouth the HRDY signal, the address strobe is invalid sets for the high-impedance state.
4 code designs
The code including the connection design’s VHDL sound code and the confirmation X86 assembly language code, the code content sees this publication website (WWW.dpj.com.cn). The VHDL code translates in Altera under Corporation’s development kit QuartusII, after downloads the electric cable downloads after FPGA, may in Debug with the assembly language to DSP carry on the read-write confirmation.
Conclusion
This article uses the VHDL language and FPGA, has designed between the PC104 main line and the DSP connection. The reason that uses FPGA, is because FPGA also contains in the system has other functional design. If only then between the PC104 main line and the DSP connection design, uses CPLD then to complete, but does not need to waste FPGA the resources.
