At present the data acquisition system develops toward high speed and the high accuracy direction. Along with the FPGA integration rate and running rate’s enhancement, may meet the high speed data gathering system’s need. The FPGA interior has the rich memory cell, easy to realize each kind of memory (for example FIFO, pair of mouth RAM and so on); Moreover, may use in based on the search table’s logical unit realizing each kind of digital signal processing (for example filter and so on), by is auxiliary the DSP processor to make each kind of pretreatment.
TI Corporation promotes the high performance digital signal processing chip TMS320C6000 series, the operating frequency is highest may achieve 1GHz, has the processing speed quick, nimble, precise and the reliable higher merit, takes in data acquisition system’s main processor, may satisfy the timely request. Based on the above consideration, Beijing gathered the audiences to reach the company to develop has used TMS320C6416 and the FPGA high speed high accuracy bi-pass magical skill according to the gathering system, each channel’s sampling rate was 3Msps, highest might reach 10Msps, the sampling precision is 14b. The system mainly includes the following several parts: High speed A/D transforms, the FIFO data buffer and the EDMA data transmission, system structure diagram as shown in Figure 1.
AD9243 and switching control
In the design uses the modulus switch chip is AD9243. AD9243 is 14 which, the 3Msps high performance modulus switch ADI Corporation produces. AD9240 and AD9243 are completely compatible, therefore system’s highest sampling rate may compatibly to 10Msps.
The modulus switch AD9243 sequential control and traditional A/D differs from, depends upon the clock controlling sampling, the transformation and the data output completely, along starts the sampling in the first clock’s rise to transform, when the fourth clock rises along the arrival, the data will appear on the D1~D14 port. This article uses the system from the circular telegram, A/D and the clock circuit is at the active status throughout, does not stop to the data carries on the transformation, reduces the error rate, increases the sampling precision.
FIFO realization and controls
In the design uses FPGA realizes the bi-pass magical skill according to the buffer and the data transmission logical control. Spartan3E is a section of high performance low price programmable logical component, has the rich logical unit and the memory cell. Its internal BlockRam may dispose for the size different each type memory, like single mouth RAM, pair of mouth RAM and synchronized FIFO, FIFO suits the memory which reads in high speed as a/D sampled data. The FIFO memory looks like the data pipeline to be the same, the data from a pipeline’s inflow, flows out from another, enters advanced the data flows out first. FIFO has two sets of data lines not to have the address wire, may write the operation in its end, but carries on another end reads the operation, data in smooth migration, thus achieves the very high transmission speed and the efficiency, because and has omitted the address wire, is advantageous in the PCB board wiring.
Uses when FIFO constitutes the high speed A/D sampling buffer, because the conversion rate is quick, if the ADC sampling’s data storage to FIFO, is after directly strict to the succession disposition request, if both succession relations coordinate improper, will have the data storage to make a mistake or to fall the number. May control the succession and the data transmission conveniently using FPGA, simple, realizes the sampling and the memory is reliably selects FPGA the merit. In this data acquisition system has only used an external clock source, direct input FPGA, after the DCM frequency division takes FIFO and the ADC clock source.
When the software design, uses the ISE development environment develops FPGA, transfers Core Generator to construct FIFO, may establish FIFO the parameter, like depth and width; Establishes FIFO each kind of sign and the control position, like spatial full, half-full entire full, midair entire spatial, programmable full and programmable spatial and so on flag bits; Writes enables, to read enables and so on control positions, with the aim of realizing with high speed A/D and the DSP logical interface. The FIFO input output pin like table shows: And WR_EN draws out by the DSP GPIO mouth, whether the control data does read in FIFO, output in the pin only to use PROG_FULL then to carry on the data transmission with DSP.
The FPGA function besides constructs FIFO to realize the data channel multiplying, but may also take cooperates the processor to carry on the real-time request high data pretreatment (for example interpolation, to average, the FIR filter and so on), reduces the DSP processing the data quantity. In the design uses the distributional algorithm the FIR filter, first transforms after ADC the data carries on the FIR filter, then stores in FIFO to wait for DSP the read. Front end FPGA replaces ASIC and DSP takes the digital signal processing operation, in the scale, the weight and the power loss aspect has reduces, moreover the volume of goods handled is higher, the development cost further reduces.
In exterior the FPGA design, must provide dodges saves saves FPGA the downloading document, after on electricity, the data will download automatically to FPGA, by will carry on the disposition to FPGA. FPGA has many kinds of collocation methods, including main string, from string, host and, from and, SPI, BPI, as well as ways and so on JTAG. The serial mode namely by the serial bit disposition, the wiring is simple, but the speed is quite slow, parallel mode namely 8 also transmit, the speed is quick, but the wiring is complex. The serial mode and the parallel mode need to dodge in addition save take the configuration files the memory. In the design this article uses C6416 multichannel buffer serial port (McBSP) to carry on the disposition by the SPI way to FPGA.
Figure 1: System structure diagram
Connection and control circuit’s design
System’s connection and the control circuit mainly include the following two parts:
1. ADC and FIFO interface circuit
Has constructed two completely same FIFO using FPGA, sends in separately two FIFO two group A/D transformation data, realizes the double channel sampled data buffer and the transmission. In the design a/D transformation clock and FIFO write the clock for the identical clock source, gets up from electricity, A/D and the clock circuit has been at the active status, does not stop carries on the data the transformation, but data whether to read in FIFO, writes by FIFO enables the signal to decide, when DSP sends out writes enables the signal is effective, transforms the data to be able to save to FIFO. May know from the front A/D sequence circuit, a/D transformation data’s output and the transformation clock have certain phase difference, may satisfies the setup time in the FPGA interior through the time delay or the clock supervisor and maintain the time, guaranteed that the data does not lose the code place to transmit in FIFO.
2. FIFO and C6416 interface circuit
C6416 has two EMIF mouths, namely EMIFA and EMIFB, the EMIFA main line width supports 64b, 32b, 16b and 8b, the addressing space is 1024Mb; The EMFIB main line width supports 16b and 8b, the addressing space is 256Mb. This article uses EMIFB to take and the FIFO connection, its main line width disposition is 16b. EMIFB may realize the seamless connection with each kind of exterior memory, like SBSRAM, SDRAM, asynchronous equipment (including SRAM, ROM and FIFO) and exterior sharing storage device and so on. In the design EMFIB and the FIFO connection selects the method which asynchronous reads, realizes the data reliable transmission, namely through realizes by /ARE and the address to two synchronized FIFO asynchronous reads, its control interface signal’s connection relations are:
RD_CLK=/ARE
RD_EN1=A20
RD_EN2=A19
Table 1:FIFO input output pin definition
In the design maps two FIFO storage spaces in EMIFB BCE2, when FIFO programmable full signal PROG_FULL is effective, initiates the external interrupt, triggers EDMA to realize the data speedy transmission. Because FIFO does not need the address wire, may produce EDMA through the simple connection to read the address, realizes EDMA time sharing to read two FIFO. Asynchronous reads FIFO to satisfy the following succession relations:
Asynchronous reads succession as shown in Figure 2, the EMFIB clock may be the external clock source, may also be obtains by the CPU clock frequency division. In the design uses the external clock source, its frequency is 133MHz, may dispose Setup, Strobe and the Hold value according to the EMIFB read-write control register.
Figure 2: Asynchronous reads the succession chart
This article subtotal
This article introduced systematically one kind the high speed system which by digital signal processor TMS320C6416, programmable logical component Spartan3E constitutes. The experiment indicated that the system has the antijamming to be strong, the reliability high, loses the code rate low status merit. In the design used FPGA to construct FIFO, might act according to the different application situation to satisfy the design requirements to the FPGA programming, therefore the flexibility was big, was one kind of good high speed data gathering plan. In addition, has used the EDMA transmission, is suitable for to apply in the timely request high each kind of high speed data gathering system. This data acquisition card uses the standard expansion bus interface, may with gather the audiences to reach company’s DEC6000 series development board connection.
