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Introduction 
     The biological chip is 20 century’s ends along with “the human genome project” the research and the development produce a high technology and new technology, is the people highly effective large-scale gain biology information effective measure. At present are majority of the biological chip to use the fluorescent dye mark testing sample member. The biological chip scanner with the laser excitation fluorescent dye, through to the shotpoint image formation, examines a spot; On the union biology chip X-Y two-dimensional precision sweep stage moves, realizes to the entire piece scanning. X-Y two-dimensional scans Taiwan’s position examination precision immediate influence to scan the resolution - - biology chip scanner performance the key parameter. X-Y two-dimensional scans Taiwan’s position examination electric circuit existence miscount based on the traditional digital circuit’s biological chip scanner and resets the question by mistake, this article by solves based on the FPGA design position examination electric circuit. Replaces traditional by the FPGA chip the digital circuit, not only may enhance system’s integration rate and the reliability, moreover the FPGA highest operating frequency has surpassed 200MHz, through the hardware description language to the FPGA programming, the circuit design is more nimble, further raised the scanning velocity and the scanning resolution for the biological chip scanner has kept a bigger allowance.

1 X-Y two-dimensional scans the Taiwan position examination principle

Figure 1 2

    X-Y two-dimensional scans Taiwan X to, Y to use the type diffraction grating to the position detecting element, 50 /mm, after special-purpose segmentation ruler 10 segmentations, survey resolution for 2μm. Opens type diffraction grating direct use electro-optic transformation principle output three-phase square-wave A, B, Z. A, the B square-wave phase difference 90° (e.g. Figure 1, 2 show), Z uses in the reference point localization, its logic level is 5V. When A square-wave in advance B square-wave 90°, indicated that the displacement direction for the direction, as shown in Figure 1; When a square-wave lags the B square-wave 90°, indicated that the displacement direction is a reversed direction, as shown in Figure 2. Scans Taiwan X to, Y to each displacement 2μm, the diffraction grating sends out one cyclical the square-wave.

    Therefore, X-Y two-dimensional scans Taiwan’s position examination first to solve to grating signal distinguishing to the question, distinguishes displacement direction which X, Y approaches; Next, for guarantee biology chip scanning when highest scanning resolution for 5μm still had the high scanning quality, X, Y direction position examination precision should be higher than 2μm, reduces scans Taiwan’s position error, must therefore further subdivide to the grating signal; In addition, but must complete the grating signal transforms the position data which the controller can read, when X approaches, Y is positive to the displacement direction, this position data increasing; When X to, Y to displacement direction for negative, this position number decreases progressively, and must guarantee that real-time accurate reliable the position data which provides X, Y to approach, as the controller (for example monolithic integrated circuit, DSP) pinpointing X-Y two-dimensional scans the Taiwan position the basis.

    In the original biological chip scanner X-Y two-dimensional scans a Taiwan’s direction position examination to use 4 frequency multiplication specific IC QA740210 to carry on to the grating signal distinguishes to, the segmentation, realizes with 4 piece of 4 binary 74LS193 counter cascade after subdividing the grating signal 16 countings, the counting value (i.e. position data) outputs through 2 piece of 8 74LS245 buffers to the controller. Thus, X, Y two direction’s position examination electric circuits reach 14 piece of chips, takes the massive PCB space, the wiring is complex, on the board crosstalk between the signal easy to cause the miscount and to reset the phenomenon by mistake, affects scans Taiwan’s pinpointing. If only uses piece of FPGA to realize the position examination electric circuit, the input is the grating signal, the output is the position data, sends in the controller directly, avoids between the PCB board the signal crosstalk, can eliminate the miscount effectively and reset the phenomenon by mistake.

2 X-Y two-dimensional scans the Taiwan position examination the FPGA design proposal

Figure 3

    Selects Spartan-II series FPGA (XC2S15-5VQ100) two-dimensional to scan Taiwan’s position examination electric circuit as X-Y, parallel to X, Y two group grating signals carries on distinguishes to, the segmentation, the counting, and provides with controller’s connection, real-time reliable X, Y transmits to the position data for the controller.

     FPGA internal module division as shown in Figure 3: From X A which, B comes to the diffraction grating two square-wave signal XA, XB by X to distinguishes to subdivides the electric circuit distinguishes after the segmentation, outputs two group signal impulse XCU, the XCD,16 position counting module separately to these two group signal impulse to carry on the counting, and two counting value XUPCNT, XDOWNCNT cancels, its difference takes 16 position data XCNT which X approaches. The interface circuit to 3 bit address signal ADDR decoding, through XCLR, YCLR to X, Y counter resets separately, and selects X approaches or Y outputs the controller to the position data. 

 To Y to similarly so. The present paper only by X approaches explains it.

2.1 distinguish to the segmentation design
    And Figure 2 may know by Figure 1, when diffraction grating to migration, A, the B level logic performance is “00″ -> “10″ -> “11″ -> “01″ -> “00″ the sequence; When diffraction grating reverse migration, A, the B level logic performance is “00″ -> “01″ -> “11″ -> “10″ -> “00″ the sequence. Therefore, so long as can distinguish these two kind of sequences, can realize distinguishes approaches.

    Introduces the exterior frequency is the 10MHz clock source, uses this clock’s rise along at the same time to A, the B signal sampling, takes current XA, the XB value, records it by two-dimensional vector AB_new, AB_new after first-level trigger, records is AB_old, AB_new and AB_old follows A, the B square-wave signal change to change, is only AB_old must lag a AB_new sampling clock cycle. Thus, may carries on AB_old and AB_new the comparison: When AB_old is “00″, if AB_new is “10″, namely The ultra B phase front 90°, XCU outputs a negative pulse, XCD maintains for the high level is invariable; If AB_new is “01″, namely A lags B 90°, XCD to output a negative pulse, XCU maintains for the high level is invariable. X changes for one cycle to the grating signal, if A ultra B 90° (displacement direction for), XCU will output four negative pulses, if A will lag B 90° (displacement direction for negative), XCD will output four negative pulses, simultaneously realized has distinguished to and the segmentation function.

2.2 reversible counter designs

    With two 16 binary counters to two group signal impulse XCU, XCD counts separately, then makes the difference with 16 single-order subtractor two counter’s counting values, the minuend is XCU counting value XUPCNT regarding this, reduces for to XCD counting value XDOWNCNT, its difference takes position data XCNT which X approaches. Thus, when XCU has the counter impulse, XCNT will increase, but XCD will have time the counter impulse, XCNT will reduce, has realized the reversible counting. Front union distinguishing to subdivides the electric circuit, causes X to position data when forward displacement increases, the reverse bearing reduces after a short while. Position data’s change has reflected the displacement situation really.

2.3 interface circuit design 
     The interface circuit is the controller real-time reads reliably X approaches the position data which or the reset connection, Y approaches. The interface circuit by the decoding circuit, the output three states of matter buffer is composed. The interface circuit and controller’s 16 bit data line CNT uses in FPGA transmitting the position data to the controller, controller’s 3 address wire ADDR takes decoding circuit’s input: Can output X, Y separately to the position data, as well as separately to X, Y to counter reset. The decoding circuit may cause X to approach, Y to the position data multiplying 16 bit data lines, highly effective use controller’s port resources; Produces the reset signal to 3 bit address signal decoding, can prevent when only uses a holding wire to disturb effectively harms the reset phenomenon which and so on reasons cause.

3 design simulations and realize
    In ISE6.1i develops in the platform, to distinguishes with the VHDL language to the segmentation, the counting, the interface circuit carries on the programming to realize. Figure 4 is the simulation profile.

Figure 4

    May see by Figure 4, X, Y to may parallel distinguish to the grating signal to, the segmentation, the counting, below only by X approaches explained: Distinguishes to subdivides the electric circuit to act according to two groups orthogonals square-wave signal XA, the XB phase difference respectively in XCU, on XCD outputs the frequency is XA, the XB4 time of counter impulse, realized has distinguished to the segmentation; Reversible counter separately to XA, XB counting, counting value difference XCNT along with X to the displacement direction’s change increases or the reduction; When controller’s address decoding signal ADDR is “101″, X approaches position data XCNT outputs to 16 bit data line CNT; When ADDR is “110″, FPGA position data YCNT which approaches Y outputs CNT; When address wire ADDR is “001″, X approaches the position data XCNT reset, the CNT performance is a high-impedance state; When ADDR is “010″, Y to the position data YCNT reset, the CNT performance is a high-impedance state; When ADDR is other random values, CNT displays for the high-impedance state, enables the controller to other peripheral device exchange data. Downloads the code after XC2S15-5VQ100, uses in the biological chip scanner, accurate reliable has realized the position measuring ability.

4 conclusions

    Realizes X-Y with FPGA two-dimensional to scan Taiwan’s position examination electric circuit, enhanced system’s integration rate fast, the position examination reliable. And, the FPGA operating frequency is high, the design is flexible, may reduce the biological chip scanner to further promote the scanning velocity and the scanning resolution development time and the cost.

Reference
1 James R.Armstrong, F.Gail Gray. VHDL Design Representation and Synthesis. Prentice Hall PTR, Inc.2003
2 Xilinx DS001 September 3,2003