Abstract: Introduced that XC2V1000 scene programmable gate array (FPGA) principal characteristic and FIR extraction filter’s principle of work, the key elaboration realizes the FIR extraction filter’s method with XC2V1000, and gives the simulation profile and the design feature.
Key word: FIR extraction filter; Stream line operation; XC2V1000; Scene programmable gate array
1 introduction
Extracts the filter widespread application in the digital receive domain, is under the digit frequency changer’s hard core. At present, extracts the filter to realize the method to have 3 kinds: Monolithic general digital filter integrated circuit, DSP and programmable logical component. Uses the monolithic general digital filter to be very convenient, but the word length and the exponent number specification are few, cannot satisfy the actual need completely. Uses DSP, although is simple, but the procedure wants the smooth execution, carries out the speed to be inevitably slow. Scene programmable gate array (FPGA) has the neat internal logical array and the rich segment resources, is suitable specially for the digital signal processing, but since long, realizes with FPGA extracts the filter to be quite complex, its reason is mainly in FPGA realizes the multiply operation effective structure deficient. Now, FPGA integrated the multiplier, enabled FPGA to have the considerable progress in the digital signal processing aspect. This article introduced that realizes the FIR extraction filter’s design method with Xilinx Corporation’s XC2V1000 FPGA.
2 XC2V1000 synopses
Virtex-ⅡThe series is Xilinx Corporation researches and develops in recent years has the high performance, the high velocity and low power loss characteristic new generation FPGA, as soon as passes through is published enjoys in public figure’s favor. This series FPGA based on IP nuclear and special-purpose module design, can for the telecommunication, radio, the network, the video frequency and the digital signal processing domain application provides the complete solution. XC2V1000 is Virtex-ⅡFamily’s, has the following main feature:
* 1,000,000 system gates;
●40×32 may dispose the logical unit (5120 slice);
●40 the 18×18 bits multiplier, in 1 work clock then completes the multiply operation;
●720Kbits RAM, but disposes (Shan Kou, a pair of mouth, to have nimbly enables or not enables and so on);
●8 DCM (Digital Clock Manager) module;
●328 user I/O.
In addition, Xilinx Corporation also provided function formidable development platform (ISE), the exploiter has been possible to complete through this platform designs completely.
3 extract filter’s principle of work
Extracts filter’s principle of work is realizes the extraction in the filter process. Is the N extraction filter speaking of the extraction rate, is not enters 1 recent data to complete 1 filter operation every time, then extracts again, but when comes in N data the filter only then complete 1 filter operation, outputs 1 filter result. After extracting filter’s result and the first filter, extracts the result is consistent, is only regarding the similar data, carries on number of times big reduction which the filter operate. Used in the number system extracts filter’s biggest merit to increase each time the filter to be possible the process time, thus achieved realizes the high speed data-in goal. Below take extraction rate as 2 has the linear phase third-order FIR extraction filter for the example to introduce that the extraction filter realize the process.
Linear phase’s FIR filter’s coefficient has some symmetrical nature [1], third-orderⅡThe kind of FIR linear phase filter may express in mathematics are
And, h(0)=h(3), h(1)=h(2). Its structure as shown in Figure 1. As seen in Figure 1, has 4 coefficient third-orderⅡThe kind of FIR linear phase filter only need 2 time addition, 2 multiplications and 2 accumulations may complete 1 filter operation. If the IPGA work clock is 80MHz, inputs x(n) the data rate is also 80MHz, then after 2 time of extractions outputs y(n) is 40MHz. That is, extracts the filter to complete 1 filter operation every time, needs 2 work clocks. If the accumulator, the multiplier sum storage can complete 1 function operation in the single clock, then only needs 1 accumulator, 1 multiplier and 1 accumulator uses the stream line operation to be possible to complete 2 time addition, 2 multiplications and 2 accumulation operations in 2 work clocks, may complete extraction filter.
4 realize specifically
4.1 structural designs
Based on above extraction filter’s principle of work, the author has realized this extraction rate with XC2V1000 is 2, has the linear phase third-order FIR extraction filter, completes the source file design together using the schematic diagram and the VHDL hardware description language. Figure 2 extracts filter’s top layer schematic diagram. And, clock is the work clock, reset is the reset signal, enable is the data-in desired signal, data_in(17:0) is the data-, data_out(17:0) is the output data, valid is the output data desired signal. addei18 is the accumulator module, mult18 is the multiplier module, acc36 is the accumulator module, signal_36-18 is the data truncation position module, fir_controller is the controller module. The controller fixed time to the accumulator, the multiplier sum storage transmission data or the control signal, realizes the stream line operation.
4.1.1 controller (fir_controller)
The controller extracts filter’s nucleus module, has 2 kind of functions: Receive data-, to other module transmission data and control signal. It acts according to the accumulator, the multiplier sum storage succession characteristic, the rule to the accumulator transmission tap data, to the multiplier transmission coefficient, to the accumulator transmission control signal, lets the duty which the accumulator, multiplier sum storage each clock completes assigns, thus realizes the stream line operation. The controller describes with the YHDL language, deposits the tap and the coefficient with the register.
4.1.2 accumulators (adder18)
Accumulator’s input and the output are 18bits, realizes with the VHDL language description. It has 2 work clock’s detention, in the data-in prepares in the good situation, the first clock obtains the additive result, the second clock saves the additive result lock the output.
4.1.3 multipliers (multl8)
The multiplier is the 18bits input and the 36bits output, realizes with storehouse part MULT18X18S and the 36bits latch. MULT18Xl8S is the XC2V1000 bringing 18×18bits the multiplier, the single clock may complete the multiply operation; the 36bits latch work in clock’s rise along, describes with the VHDL language. The multiplier (mult18) also has 2 work clock’s time delay, in the data-in prepares in the good situation, the first clock obtains the multiplication result, the second clock saves the multiplication result lock the output. The accumulator and the multiplier use the lock to save the output the structure, although increased 1 work clock’s detention, but is advantageous in extracting the filter stable work, enhances the reliability.
4.1.4 accumulators (acc36)
the 36bits accumulator uses in accumulating multiplier’s output, obtains the filter result. It has 1 control port clr, when clr is the high level, outputs the preceding round accumulation result, and the initialization starts new one round the accumulation; When clr is the low level. Carries on the accumulation operation. The accumulator describes with the VHDL language.
4.1.5 data truncation position (signal_36-18)
The data truncation position describes with the VHDL language, uses in carrying on accumulator’s 36 outputs choices processing, generally the truncation falls the data low position part, the retention data top digit. For to extracts the filter to carry on the function simulation, here truncation falls data high 18, retention data low 18.
4.2 work processes and function simulation
The accumulator, the multiplier sum storage each clock must complete the task which under controller’s function assigns, thus forms the stream line operation, realizes extracts the filter.
Below take extracts the filter to complete 1 extraction filter’s entire process as the example, the explanation extraction filter’s work process. The supposition clock 1, clock 2, clocks 3 and the clock 4 controllers have received the data x(n-3), x(n-2), x(n-1) and x(n), that
Clock 5: Controller to accumulator transmission data x(n) and x(n-3);
Clock 6: The accumulator carries on. x(n) x(n-3) operation; Controller to accumulator transmission data x(n-1) and x(n-2);
Clock 7: The accumulator carries on x(n-1) x(n-2) operation, outputs x (n) x(n-3) operation result. Controller to multiplier transmission coefficient h(0);
Clock 8: The accumulator outputs x(n-1) x(n-2) operation result, the multiplier carries on the h(0)[x(n) x(n-3)] operation, the controller to the multiplier transmission coefficient h(1);
Clock 9: The multiplier carries on the h(1)[x(n-1) x(n-2)] operation, outputs h(0)[x(n) x(n-3) 1 operation result. The controller to the accumulator transmission control signal (clr is high level);
Clock 10: The multiplier outputs the h(1)[x(n-1) x(n-2)] operation result. The accumulator initialization starts to accumulate the operation. The controller to the accumulator transmission control signal (clr is low level);
Clock 11: The accumulator carries on the accumulation to operate h(0)[x(n) x(n-3)] h(1)[x(n-1) x(n-2)]. The controller to the accumulator transmission control signal (clr is high level), the controller output filter data desired signal (valid is high level);
Clock 12: The accumulator outputs the h(0)[x(n) x(n-3)] h(1)[x(n-1) x(n-2)] accumulation result, and the initialization starts the new round accumulation operation. The controller output filter data invalid signal (valid is low level);
The above is extracts the filter to complete 1 extraction filter’s entire process. Obviously, inputs from data x(n) to the filter result y(n) output needs 8 work clocks. If the controller does not stop to the accumulator, the multiplier and the accumulator transmission tap, the coefficient and the control signal, will form the stream line operation, then every 2 clocks, will extract the filter to output 1 filter result. Figure 3 extracts filter’s simulation oscillogram, establishes coefficient h(0)=1 and h(1)=2 in the controller.
4.3 matters needing attention
2 n binary number adding together, its and needs the n l position binary number to be able at least to express correctly. In this design’s accumulator input output is 18, to prevent the accumulator to overflow, should guarantee that 18 data-in x(n) the highest 2 phases with (are sign bit).
In order to realize extracts filter’s multistage series structure, should unify data-in desired signal enable and the output data desired signal valid succession request. This design stipulation controller after accumulator output filter result number the next 1 clock sends out the filter result desired signal, when the width is 1 work clock cycle.
5 design features
Uses this design structure to realize extracts the filter to have the following 3 characteristics:
(1) saves the internal resources and raises the resources use efficiency
Xilinx Corporation for the convenience user design filter, integrated the general digital filter’s design in the IP nucleus, but often cannot aim at the actual situation using the IP nucleus formation’s digital filter to use the internal resources reasonably, creates the resources waste. In this design has used the running water line structure, all functional module full load work, does not have the free time to wait for the clock, thus has saved the internal resources, raised the resources utilization ratio.
(2) may realize extracts the filter multistage structures
In view of extracts filter’s input level, may adopt the same design method re-engineering first-level extraction filter, extracts the filter once more before the first-level output’s data, thus realizes the multistage extraction filter structure.
(3) design is flexible, and extended
Are suitable with the register depositing tap and the coefficient for the filter exponent number few situations, if needs to use over a hundred steps the extraction filter, easiest to use internal: RAM depositing tap and coefficient, by now so long as modified controller’s logical design already to be possible slightly to realize. Based on this, but may also realize extracts the filter programmable.
6 concluding remark
This article take realizes the extraction rate as 2 has the linear phase third-order FIR extraction filter is the example, introduced one kind realizes the FIR extraction filter’s design method with XC2V1000 FPGA. Is strong with this methods design extraction filter flexibility, the availability of resources is high, can widely apply in the digital receive domain.
