1 introduction
It is well known, under the complex background condition, must carry on the infrared tracking, the survey to the small and weak goal is a difficult problem effectively accurately. In this kind of situation, because the goal and the background contrast gradient is small, the signal-to-noise ratio to be low, if carries on the track, the survey quite to be often difficult directly, must therefore carry on the filter pretreatment first to the image signal, achieves suppresses the background noise. Increases the target strength, thus enhances the image signal-to-noise ratio the goal, builds the good foundation for the following work.
In real-time image processor, signal pretreatment including to image each kind of filter, histogram statistics and balanced, image intensification, gradation transformation and so on, their common feature is processes the data quantity to be big, if will realize with the common software will be quite inevitably slow. But regarding some timely request quite high system, the processing speed often is the key aspect which must consider, once the speed cannot follow, timeliness also without knowing where to begin mentions. In view of the image pretreatment stage operation structure quite simple characteristic, carries on the hardware with FPGA to realize is the ideal choice without doubt, has like this simultaneously given dual attention to the speed and the flexibility, lightened the DSP burden greatly.
This system uses Verilog the HDL language. Improves the algorithm using one kind of fast value filter to carry on the design to the electric circuit, and Stratix II EP2S60F67214 which produces by Altera Corporation FPGA chip for hardware platform. This component has inherited Altera the Corporation Stratix II series common merit, because has introduced brand-new auto-adapted logic module (ALM), enables Stratix II to have a higher performance and the logical seal, a less logic and the wiring progression as well as the stronger DSP support, but Stratix II EP2S60F67214 is are more than 18% component logic Xilinx Corporation’s similar component Virtex-4XC4VLX60, including 51 182 register positions, 2 544 129 memory positions as well as 48 352 ALUT, this component fruitful in resources, only need take the very small part to realize the value filter, leaves leeway more spaces for the following design’s growth.
2 value filter’s basic principle and improvement algorithm
2.1 value filter’s basic principle
The value filter are by the Tukey invention one kind of misalignment signal processing technology, the early time use in the univariate signal processing, afterward was very quick is used the two-dimensional digital image smooth, was one kind suppresses the image noise effectively, enhanced the image signal-to-noise ratio the nonlinear filter technology. It is one kind of neighborhood operation, is similar in the convolution, but calculates is not the weighting summation, but carries on the neighborhood in picture element according to the gradation level sorting, then chooses this group the intermediate quantity to take the output picture element value. Compare with the average value filter as well as other linear filter, the value filter’s prominent characteristic is while filters the impulse noise/pulse noise/pulsive noise well (Impulsive Noise) and the spiced salt noise (Salt and Pepper Noise), but can also the protected object picture edge outline thin song S mildew type expression be? br>
g(x, y)=median{f(x-i, y-i)},(i, j)∈S (1)
In the formula g(x, y), f(x, y) is the picture element grey level, S is the template window.
But the value filter realize the process are generally specifically:
(1) chooses a (2n 1)×(2n 1) sliding window (usually is 3*3 or 5*5), causes it along the image data line or a row direction by the picture element glide (usually to from left to right, from top to bottom chase a line of migration).
after (2) each time skids, the gemel window inside the mouth’s picture element grey level carries on sorting, replaces the window central place picture element with the sorting obtained intermediate quantity the grey level.
2.2 middle finger filter’s improvement algorithm
The value filter’s algorithm are many, but the usual data sorting quantity is big. Needs to consume the massive time, does not favor the imagery processing timeliness. This article uses one kind of window size is the 3*3 fast sort algorithm. Reduced the sorting quantity greatly.
For ease of explanation. The 3*3 window’s in each picture element distinction definition is M11, M12, M13, M21, M22, M23, M31, M32, M33. Picture element arrangement like table 1.
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First to the window each line of computation maximum value, the value, the minimum value, like this altogether may obtain 9 values separately, includes 3 maximum values, 3 values, 3 minimum values separately:
The first line of maximum value: Max1=max[M11, M12, M13];
First line of value: Med1=med[M11, M12, M13];
The first line of minimum value: Min1=min[M11, M12, M13];
Ex analogia:
Max2=max[M21, M22, M23]; Med2=med[M21, M22, M23]; Min2=min[M21, M22, M23];
Max3=max[M31, M32, M33]; Med3=med[M31, M32, M33]; Min3=min[M31, M32, M33];
In the formula, max indicates takes the maximum value, med indicated that takes the value, min indicated takes the minimum value.
It is not difficult to judge, in 9 values. in 3 maximum value’s maximum values and 3 minimum value’s minimum value is certainly in 9 picture element maximum values and the minimum value; in 3 value’s maximum values are bigger than 5 picture elements at least: Namely in line of business minimum value, other 2 line of value and minimum value: But in 3 value’s minimum values are smaller than at least 5 picture elements: Namely in line of business maximum value, other 2 line of value and minimum value. Finally, the intermediate quantity which obtains compared with 3 maximum value’s in minimum value Min_of_Max,3 in value’s value Med_of_Med,3 in minimum value’s maximum value Max_of_Min. namely for filter’s final output Med_of_nine. The concrete process expression is as follows:
Min_of_Max=min[Max1, Max2, Max3];
Med_of_Med=med[Med1, Med2, Med3];
Max_of_Min=max[Min1, Min2, Min3];
Then final filter result:
Med_of_nine=med[Min_of_Max, Med_of_Med, Max_of_Min];
Only needs 17 comparisons using this kind of rank order method’s value filter operation, compares with the traditional algorithm. Reduced nearly 2 times compared with the number of times, and this algorithm is suitable in makes the parallel processing on FPGA, raised filter’s speed greatly.
3 value filter hardware circuit design
The key must complete 2 modules the designs, respectively is:
3.1 3*3 window module
Realizes the two-dimensional value filter with the hardware, a very important spot is can save the real-time image data reliably, and causes the time delay to be shortest. In order to satisfy the timely request, carries on the entire frame pretreatment to the image, but this kind of entire frame pretreatment will not be will put in order the first frame image data will preserve completely after the memory to the entire frame image data carries on processing again, but then after will be will save the n-1 good image data, starts to process, n will be the window size. In this design, selects the 3*3 window the value filter, namely n=3. Such design’s advantage is, FPGA may realize this module by the serial running water way, has saved many time, was the real-time processing has created the advantage. Figure 1 gives in the 3*3 window the value filter hardware diagram.
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In Figure 1, D represents the delayer, FIFO represents advanced leaves the memory first. This advanced leaves memory module as shown in Figure 2 first, wrreq and rdreq respectively be write, read enable, aclr is the asynchronous reset. The image data inputs in turn by the picture element clock metre from the data input end, FIFO uses for to save a line of data, thus causes M11, M12,…, M33 happen to correspond the 3*3 window 9 image data (to see Table 1). When the data stream inputs unceasingly from the data input end, the 3*3 template corresponds the image data with is changing unceasingly, like this may carry on 3*3 template processing to an image all picture element.
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in 3.2 3*3 windows 9 value sorting modules
Improves the algorithm by front 2.2 to the value filter the explanation not to be difficult to see, the entire sorting is actually must carry on 7 time 3 value comparisons:
1) 3*3 window each line of 3 integers carry on the comparison. Obtains each line of maximum values separately, the value, the minimum value, altogether some 3 lines, need 3 time 3 value comparisons;
2) 3 maximum value groups, the value group, the minimum value group carry on 3 value comparisons, 3 groups need 3 time 3 value comparisons;
3) in the maximum value group’s minimum value, in the value group’s value, the minimum value group’s maximum value 3 integers carry on a comparison again. Needs 1 time 3 value comparison.
For as far as possible nurse resources, use in the hardware design fully ” the module multiplying ” the principle, only need design a simple 3 value comparator module first, 7 times transfers this module namely to be possible with ease to complete value filter sorting.
Moreover, in image each edge. Because is unable with the 3*3 window cover (a window part to cover image exterior). Therefore is unable to transfer this value filter sorting module directly. Has referred massively based on the domain image hardware processing system’s procedure. This article supposes simply the picture edge picture element ” 0 “. Will not affect the entire value filter’s effect. This only need add a judgment window position again the module, if the judgment result is an edge. Then does not transfer the sorting module ” 0 ” to bestow on directly the out-port; Otherwise. Then transfers this sorting module.
4 based on FPGA processing result
The entire electric circuit’s design uses Verilog the HDL language compilation, take Altera Corporation’s Stratix II EP2S60 component as the hardware platform, realizes 320*256*16 under the Quartus II 5.1 software development environment the bit gradation image value filter. This image 1 time is 20ms (its middle place blanking time approximately is 6.35 ms), the picture element clock is 6 MHz, the algorithm takes resources as shown in Table 2.
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As seen in Table 2, this value filter design’s chip resources occupancy rate is very small, therefore the major part resources may use in the following development design. Processes a data to need the time approximately is only 4.2 ms, satisfies the overall system completely to the speed high request. But in the same 3×3 template the value filters Prajnya to process on ADI TS201 DSP, needs the time approximately is 15.3 ms. Obviously, realizes the infrared imagery value filter based on Stratix II EP2S60 compared to realize based on TS201 has a better timely superiority, moreover this design has used the fast value filtering algorithm, therefore saved more time compared to the traditional algorithm, the resources occupancy rate is also small. The input, outgoing picture distinction like chart 3, shown in Figure 4, because this filter module sets at the edge is 0, therefore the chart edge is a heavy line. Around the contrast the image may see the value filter to have the very good filter action to the spiced salt noise.
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5 concluding remark
This design proposal has used one kind of improvement fast value filtering algorithm, realizes the entire digital infrared imagery filter successfully on Altera Corporation’s high performance Stratix II EP2S60, during guarantee timely, causes the hardware volume is the deflation greatly, reduced the cost greatly, has the very strong use value. If recombination other filter pretreatment method, then may further enhance its filtration noise ability, improves the picture quality well. This design proposal can only utilize in the matrix 3*3 template, regarding other type’s template (for example the 5*5 template, cross linear template), needs to carry on the system design. Moreover. In the FPGA design, wants certainly the strict control succession, guaranteed that the clock has the enough setup time and maintains the time, and guaranteed that the succession the strict synchronization, electric circuit’s time delay should be as far as possible small.
