Abstract: Introduced that the numerical control oscillator’s principle of work, the key elaboration realizes the numerical control oscillator’s method with scene programmable gate array (FPGA) and static stochastic memory (SRAM), simultaneously gives uses this structural design the numerical control oscillator’s characteristic and the performance.
Key word: Numerical control oscillator (NCO); Search table; XC2V1000; CY7C1021; Design
Chinese Library classification number: TN914.3 document code: A article serial number: 1006-6977(2006)01-0022yi03
1 introduction
The numerical control oscillator is in the digital communication modulates the demodulation unit essential part, simultaneously is also each kind of digit frequency synthesizer and the digital signal generator core. Along with digital communication technology development. To transmits the data the precision and the speed request is getting higher and higher. How to obtain may the numerical control high accuracy radio-frequency carrier signal realizes the question which the high speed figure communications system must solve. The programmable logical component and mass memory unit’s development has brought the dawn for this question’s solution. This article introduced how to use FPGA (the scene programmable logical gate array) and SRAM (static stochastic memory) realizes the high accuracy numerical control oscillator.
2 NCO outlines
NCO (Numerical Controlled Oscillator) is the numerical control oscillator uses in having the controllable sine wave or the cosine wave. It realizes the method mainly has the computation method and the table look-up law at present and so on. The computation method produces the sine wave sample by the software programming’s way through the real-time computation. This method time-consuming many, and can only have the frequency relatively low sine wave. But needs to produce time the high speed quadrature signal, is unable with this method to realize. Therefore, uses generally in the practical application is most effective, the simple the table look-up law, namely acts according to each NCO sine wave phase to calculate the good phase beforehand the sine value. And takes the address by the phase angle this phase sine value data storage in the table, then has the address message read current time phase value through the phase accumulation the sine value which corresponds in the table, thus produces needs the frequency the sine wave.
Realizes the NCO performance index with the table look-up law to be decided by the table look-up depth and the width, namely is decided by the expression phase data figure (table look-up memory address wire figure) and the expression sine value data figure (table look-up memory data line figure). Improves the NCO performance simple and the most basic method is enlarges the search table the depth and the width. At present, realizes the NCO universal procedure with the search table law is takes the search table with internal ROM, as a result of the internal resources’ limit, the search table’s depth and the width will not be big (usually will be generally 256×8 bits), has limited the NCO performance enhancement greatly. Takes the search table with independent large capacity SRAM, from internal transfers to outside the piece the search table, may good solve this problem. Based on this thought that the author successfully (Xilinx Corporation’s XC2V1000 gate array) and SRAM (Cypress Corporation’s CY7C1021 memory) has realized NCO with FPGA.
3 NCo realizations
3.1 structural designs
NCO structure as shown in Figure which realize with FPGA and SRAM 1. In the big frame the part is completes by FPGA. The major component divides into the frequency control word register, the phase control word register, the channel control word register, the accumulator, the accumulator, the channel selector and the latch and so on. The microprocessor carries on the control to NC(), the available monolithic integrated circuit or DSt, (digital signal processor) realizes.
3.1.1 frequency control word register, phase control word register, accumulator and accumulator
The frequency control word register and the phase control word register is 32 bit parallel input, the parallel output register, they carry on the read-write through the microprocessor connection. Frequency control word register determination carrier frequency. Phase control word register determination carrier starting phase. 32 accumulators to carry on the accumulation operation on behalf of the frequency frequency control word, the accumulation result with represent the starting phase the phase control word to carry on the additive operation through 32 accumulators. Additive result high 16 bit data read search table address message. The frequency control word register, the phase control word register, the accumulator and the accumulator may use VHD [. The language describes, integrates in a module, its VHDL source program is as follows:
3.1.2 channel control word register and channel selector
The channel control word register and the frequency control word register and the phase control word register’s structure is completely same. Is 32 bit parallel input/parallel output register, carries on the read-write through the microprocessor connection. The channel control word register only uses last to carry on the control to the channel selector. The channel selector is two chooses a multiplexer. When the Sel control end is O selector channel l, when the Sel control end is 1 selector channel 2. The channel selector takes SRAM and the FPGA connection. Each channel not only includes 16 address wires, moreover also has 3 pilot wires and 32 data lines. In chart l, to cause NCO the structure to be clearer, the channel selector’s pilot wire and the data line have not expressed.
3.1.3 SRAM and latch
SRAM is 64Kx32 high performance static state RAM. by 2 CY7C102l(64KXl6) parallel constitution, serves as the search table. SRAM carries on the disposition through the microprocessor, deposits 2 group, 1 cycle, 65 536 16 carrier samples directly (high 16 depositing sine wave, low 16 depositing cosine wave). Although SRAM is the asynchronous component, but because the working speed is extremely high, definitely may work under the simple control logic coordination under the synchronized pattern. When NCO work. The control logic (with VHDL language description) causes SRAM through channel l the control holding wire to be in reads the active level, enters 32 latches with phase address direct drive SRAM. from the SRAM read-out’s data. Divides 2 group direct output. Does not need any address and data conversion logic. Uses in latch’s clock and uses in the accumulator, accumulator’s clock differing on the phase 180°, this is decides by the SRAM switch characteristic.
3.2 NCO work processes
Before the NCO work, must carry on the initialization to SRAM. Figure 2 shows NCO the work flow. First, the microprocessor reads to the channel control word register 1, causes the channel selector choice microprocessor connection. Then. The microprocessor carries on the disposition to SRAM. Reads in the carrier sample to SRAM. Then, the microprocessor reads in the frequency control word and the phase control word to the frequency control word register and the phase control word register, definite carrier frequency and starting phase. Finally, reads in 0. channel selector selector channel l to the channel control word register, causes NCO to be at the active status. This time the microprocessor may carries on the dynamic read-write to the frequency control word register and the phase control word register, realizes to the NCO tendency real-time control. Completes the NCO frequency and the starting phase adjustment.
3.3 NCO performance appraisal
According to the above structure. The author has designed one kind of NCO system. This system’s work clock is 80MHz. takes the microprocessor with DSP. Through system test. This NCO performance index has achieved the design requirements, the frequency resolution △f=O.0186Hz, signal-to-noise ratio (SNR) above 100dB. Figure 3 shows NCO the typical characteristic curve.
4 unique features
Realize the numerical control oscillator with FPGA and SRAM to have many characteristics.
First, the search table’s capacity may further enlarge. This design’s structure separates the phase accumulation part and the search table realizes alone. Because FPGA has may duplicate the programming, and has the rich I/O resources, so long as therefore modifies in FPGA the logical design to be possible slightly external larger capacity SRAM.
Next, the carrier sample’s data figure may control nimbly. In search table capacity certain situation, may act according to the concrete application adjustment carrier sample the data width. Realizes the method has two: First, when to the SRAM disposition through microprocessor by software programming way positive governing SRAM data width: Second, carries on truncation position processing in FPGA to the SRAM output data’s figure. May through adjust in FPGA latch’s output to realize.
Third, can apply in nimbly other domains. This NCO only consumes in FPGA 6% Slices resources, the massive resources do not have including internal RAM and the hardware multiplier are useful, uses these resources to be possible to carry on the function to NCO to expand, realizes under the digit the frequency changer (Digital Down Converter-DDC), the digit frequency synthesizer (Direct Digital Synthesizer-DDS) and the modem and so on.
5 concluding remark
This article introduced one kind of new NCO realizes the method, may realize with this methods design’s NCO to the carrier frequency, the phase and the scope complete control. Because takes the search table with independent large capacity SRAM, enables NCO to have the high precision. Simultaneously this NCO has the very big display space, can utilize other domains nimbly.
