0 introductions
The phase lock technique has the widespread application in the commercial measurement and the control domain, its essence is one kind of phase negative feedback system. In the online -like UPS system, the invertor and the city electricity may regard as are two potential sources, between the two has the cut the process, because cuts the switch is not ideal, the cut requires certain time, is possibly inconsistent in the cut instantaneous the two’s output wave shape. On the one hand the profile difference will bite can create the power supply the interrupt, on the other hand possibly will also have between two potential source circulations, will specially use the static switch will cut, easy to create component’s damage. In order to guarantee that the cut process the security, must output the invertor with the city electric output phase-lock, enables the two to have the same phase and the peak-to-peak value. Same truth, phase-lock synchronization when many UPS and machine and many UPS constitute the redundant system is also essential. The UPS invertor output phase may maintain consistent with the city electricity, but output wave shape’s scope must maintain then has violated the UPS function identically, therefore, usually the UPS phase-lock’s goal is in the situation maintains the scope approximately equal at the guarantee phase coincidence.
1 digital phase-lock’s algorithm
Realizes the phase track means to be many, one method is takes the synchronized signal with the city electricity voltage, this method realizes is quite simple, may in a short time lock the phase, but because the city electricity voltage is not the standard sine wave. Will cause the frequency to have the deviation. The commonly used phase-lock way is the military and political leader potential difference transforms into the voltage, uses this voltage to control a pressure again to control the oscillator to realize. Simulation phase-lock (APLL) and the digital phase-lock (DPLL) basic structure is similar, including discriminator (PD), the low pass filter, the pressure controls/the numerical control oscillator (VCO/DC0) and the frequency divider 4 parts, as shown in Figure 1. The digital phase-lock realizes has many methods, for instance monocycle digit PLL control and so on.
Regarding UPS, the basic phase locking circuit may obtain one with the input voltage phase frequency consistent signal really φo, then φo adjusts invertor’s reference sine wave voltage signal by the signal. Its result is, the output voltage may maintain with the input voltage the frequency is consistent, but has a fixed phase difference. This is because the invertor sampling link, is adjusted the link, to output the filter and the load and so on many factor influence results. This article uses the PLL structure like chart in 2 dashed line frame shows, input phase letter φi for city electricity phase, feedback phase signal φc for invertor output capacity voltage phase.
The discriminator outputs one to become the proportional relationship with the phase difference the result, the scale-up factor is Kd, then has
Filter’s pulse transfer function supposes is F(z), may use Butterworth, the agreement to compare filter and so on snow husband, also often uses the proportion integration element or other links replaces the low pass filter. What this article uses is a proportion integration element, namely
Here, the numerical control oscillator has borrowed the ordinary practice use name, in fact not a vibration part, but is a proportion amplifying element, after φf the proportion enlarges, obtains the phase-lock output signal cycle with the input signal cycle (Tin) adding together To=Tin Koφf, the output phase for φ=Koφf supposes the phase-locked loop exterior link pulse transfer function is G(z), then overall system’s pulse transfer function is
In this UPS, by the actual electric circuit and the procedure determined that C(z) the expression is quite difficult, design time may according to invertor’s simulation result determine approximately G(z) is a time delay very small sluggish link or simply neglects its influence.
2 use the digital phase-lock which DSP realizes
In phase-lock’s link only then the discriminator phase examination is completes by the hardware circuit, other realize in DSP by the software. Phase examination’s electric circuit as shown in Figure 3, comparator U2B and periphery some primary devices constituted one to bring back to the difference the zero crossing comparator. Returns to the difference the size mainly to be decided in the antijamming considered, when invertor switch to control circuit’s disturbance is very serious, requests the difference to obtain greatly to well, but oversized will return to the difference to cause the phase examination error to increase, therefore, will return to the difference size the choice to need to fold the turban consideration. In actual electric circuit. Nearby because the zero crossing disturbs the existence, the output is section of levels in “0″ and “1″ between repeatedly the high frequency turn over signal, therefore, needs to carry on processing which in the procedure phase examination vibrates.
The frequency size in the procedure is by two zero crossing signal between counting value determined that is also the cyclical value which expressed with the juice value. The counting carries on each interrupt cycle one time, each counting’s unit represents 50μs, 20ms is 400 Units of measurement, the phase difference is also obtains by the counting. The procedure before carrying on the phase-lock must judge the city electricity the frequency whether in normal scope, if has surpassed the scope, then does not track the city electricity to use own oscilation frequency to determine invertor’s output frequency, at this time the invertor output frequency is precision very high 50Hz, but does not allow to carry on the operation which the bypass cuts. In order to prevent the invertor output frequency oversized or too small, must to output cyclical the computed result to carry on the scope limit. Simultaneously should also limit withers the entire scope size, avoids outputting the frequency the fierce change.
The PLL subroutine also included Figure 2 the reference waveform to have the part finally, entire procedure flow as shown in Figure 4.
3 experimental results
Realized the invertor with the above method in TMS320F240 to output with the city electricity input phase-lock, phase-lock’s result pats by the TDS210 oscilloscope, as shown in Figure 5. Figure 5 scope high 2 for invertor output voltage profile, obtains with 100:1 probe head, scope low 1 for input city electricity profile, is simultaneously obtains with 500:1 difference probe head (as a result of the oscilloscope not 500:1 probe head establishment. When survey this channel treats as is 1:1 probe head, therefore, in fact the profile 1 correspondence’s oscilloscope measurement is 250V/div, but is not 500mV/div which in the chart demonstrated).
May see phase-lock’s process clearly from Figure 5, initial time invertor output leading of phase Yu Shidian, therefore, locks the input voltage phase gradually with the quite big output cycle, after the locking, the input voltage same cycle output, has realized the frequency synchronism.
4 conclusions
This article analyzed and discussed in invertor’s digit phase lock technique, and has realized invertor’s digital phase-lock with DSP, might see from the experiment profile, this method solved the voltage synchronization phase-lock’s problem well, the circuit structure has been simple.
