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Abstract: Along with the chip integration rate’s enhancement, some function complex system chip power loss’s management, already brought to everybody more and more attentions, how to control good SoC the power loss to become the important attribute which whether the chip will succeed. This article proposed that one kind through the dynamic management clock’s strategy, achieves reduces the entire SoC chip power loss the goal; At the same time, in the analysis dynamic management clock plan will possibly appear some questions, and will give the solution. Key word: System chip burr AMBA main line time lag Introduction 牐 犓 the widow occasionally becomes the electric circuit technology the swift development and to expends class the electronic products - - specially is portable (migration) face the customer electronic products demand, impelled SoC (System on Chip) swift development, also proposed many new topic [1] to the people. SoC chip which actuates regarding the battery, has not been able only to consider again it optimizes spatial two aspect - - speed (performance) and the area (cost), but must pay attention to it already to display and became more and more important third aspect - - power loss [1], like this could lengthen battery’s life and the electronic products running time. Figure 1 In SoC the CMOS electric circuit power loss includes: First, the static power loss, is mainly by the static electric current, leaks factors and so on electric current to create; Second, the dynamic power loss, is mainly by the electric circuit when the signal translation creates the transient state open-circuit current (crowbar current) and the load current (load current) and so on factors create [2], it is in the SoC chip power loss important source [3]. How to reduce in SoC the power loss, can obtain the different solution from the different stratification plane analysis. (Architecture) the angle considered from the chip system-level that has the low power loss main line design, the low power loss memory system design, the low power loss clock network design, development system’s rest pattern, the clock gating and so on technologies; (RTL) the angle considered from the chip behavior level that before having the signal gating, pre-, to calculate, the operand separation, the state machine to optimize, parallel and technologies and so on running water structure; (Gate) the angle considered from the chip gate level that has the cushion to insert, technical [4] and so on extraction factor, unit reproduce by pantograph, base pin exchange, phase disposition. Considers the power loss question from a higher abstract level, the scope which the chip power loss optimizes to be more remarkable. This article proposed based on the dynamic disposition clock’s SoC low power loss management is from the chip system-level angle consideration. In the final experiment, it reduced the entire chip power loss very obviously. 1 dynamic disposition clock’s SoC low power loss management principle Based on the microprocessor application’s SoC design, its complex degree change is very big: Possibly needs to use all hardware source in some applications, but possibly only needs in other applications to use a part of hardware source; In some applications possible need very high operating frequency, but actually may cut the operating frequency greatly in other applications. The tendency manages the SoC system clock’s thought is: Not only dynamic manages the SoC internal module the clock source supplies, but may also dynamic dispose the SoC system’s clock rate. Dynamic manages the SoC internal module the clock source supplies is, according to the different application, manages the SoC internal hardware source. In brief, carries on the operation which the internal module opening and closes. The closure single module, may through establish one to each module to enable the position, then enables the position programming to this to achieve the closure or to open that module. But does this is not best, the reason has two: First, each module’s connection part must be opens throughout, otherwise, the CPU nucleus is unable momentarily to carry on the programming to its internal register; Second, enabled the position through the module only to close its function operation, but has not closed its module’s in clock tree, i.e. inside it the clock tree was still at the state of activation, but the clock tree created the power loss occupied the single module dissipation the very major part. Actually the majority modules are the synchronous system, system’s all operations are [5] which carries on under clock signal’s metre, closes the clock source to be able simultaneously to achieve the closure module and to reduce the power loss the goal. Dynamic disposes the SoC system’s clock rate is take does not sacrifice system’s performance as the premise, the dynamic management system management system’s operating frequency reduces SoC the power loss. The clock rate is the influence dynamic power loss important attribute: [3]. Its operating frequency is higher, the power loss is also bigger. But when many, all modules are not the work in the identical clock rate, or the identical module may work in the different time interval in the different clock rate. These are dynamic dispose the SoC system’s clock rate premise. Figure 1 is in the entire SoC clock network (clock tree). In the chart power loss administration module (power management module) completes this kind of function. Figure 3 2 chip low power loss job management patterns To realize the dynamic disposition clock’s SoC low power loss management games well, the chip developed in its low power loss management mechanism four kind of working pattern in its work: Slow, Normal, Idle and Sleep. Following union shown in Figure 2 the working pattern flow chart shows its working mechanism. Table 1 is four kind of working pattern condition. Table 1
(1)Slow pattern When system reset later or when the system switches off PLL not to need the high speed clock moves, the system enters to the Slow pattern. Under the Slow pattern, in system’s CPU nuclear and all module’s clock source comes from the crystal oscillator. If the system thought by now has the necessity to switch off certain modules, that may through the disposition power loss administration module internal register, enable the corresponding module clock source the position to switch off. (2)Normal pattern If needs the high speed clock in certain applications, then should cut the Normal pattern. Under the Normal pattern, in system’s CPU nuclear and all module’s clock source comes from PLL. Certainly, may also switch off certain modules under this kind of pattern according to system’s application. If the system needs to adjust clock’s frequency, may through dynamic dispose PLL to realize. But in dynamic disposes in the PLL process, must pay attention to this kind of question: Because PLL has the time which a clock locks, during this period of time, it outputs the clock profile is anomalous, this time cannot use it to take the chip the clock source. For guarantee system’s normal operation, may cut temporarily system’s clock source the crystal oscillator condition, will wait PLL the clock to output stable later to cut again system’s clock source the PLL condition. (3)Idle pattern If the CPU nucleus already processed all duties under the current condition, will be at the idling condition in very long period of time, then the system should enter to the Idle pattern. Under the Idle pattern, will only close the CPU nucleus the clock source, but all modules will maintain the original conditions. But under this kind of pattern, cannot dynamic dispose PLL, by obtains the different clock rate; May also not dynamic manage various modules the clock source, because of this clock Core the dormancy, it had already not had the means to carry on the disposition to the power loss administration module internal register. Regardless of the preceding condition is the Slow pattern or the Normal pattern, the system may enter to the Idle pattern under; But when the system withdraws from the Idle pattern, it should return to the preceding working pattern. When the system needs the CPU nucleus carries on business processing, may through one awaken the signal to let the system return to the Slow pattern or the Normal pattern. If the overall system already handled all business, and will be at the idling condition in very long period of time, then the system should enter to the Sleep pattern. Under the Sleep pattern, closes the CPU nucleus and all module clock source. Although may cuts from the Slow pattern or the Normal pattern to the Sleep pattern, but when it withdraws from the Sleep pattern, the system can only return to the Slow pattern. Because to further reduce the entire chip the power loss, when the Sleep pattern will simultaneously close PLL, therefore when it will withdraw can only return to the Slow pattern, will then the basis current application decision have cuts the Normal pattern again the necessity. When the system needs to carry on business processing once more, may awaken the signal through one to awaken the entire SoC chip system. 3 power loss administration module realization The power loss administration module mainly by a state machine, some multi-channel selectors and some gating clock circuit is composed. State machine’s responsibility duty is completes between each kind of pattern the cut and sends out PLL the control signal. The multi-channel selectors mainly complete between each kind of clock source the choice, but the gating clock circuit completes the CPU nucleus and various modules clock source open with the shutting down function. Figure 3 is in the power loss administration module the clock source route. May see clearly from Figure 3, in power loss administration module illustration two PLL: One is advocates PLL (MPLL), it provides in entire SoC besides the USB module all module clock source; Another this time PLL (UPLL), it only provides the clock source to USB. MUX completes the crystal oscillator clock and the PLL clock’s choice, the clock which selects (FCLK) is simultaneously delivered the CPU nucleus, HCLK and PCLK, then gating sends out the clock source according to each module’s need. This is based on AMBA bus structure SoC. According to the AMBA main line’s agreement, on the CPU nucleus, on the AHB module and the APB module’s clock rate may dispose the ratio to relate [6] doubled and re-doubled. Only provides to AHB on after the HCLK frequency division’s clock source the module, but only provides to APB on after the PCLK frequency division’s clock source the module. AHB_con, APB_con, Core_con and USB_con manage the SoC internal module together the clock source supplies. in 4 dynamic clock management’s question and eliminates the method Dynamic disposes overall system’s clock rate, although may control the good entire SoC chip very conveniently the power loss, but simultaneously also has brought some negative influences. In the power loss management unit’s multi-channel selectors and the gating clock circuit is most has the possibility to produce the burr, but the burr to the synchronization number system is fatal. It will cause synchronized the defeat, the data loss, the register to enter the metastable state, what will be more serious, will cause the entire synchronous system’s function defeat. The burr production is because these input signal’s succession match had the problem, according to the order which decides has not appeared, or these signals install the transformation the opportunity not to be inappropriate. Therefore when the RTL design must guarantee that achieves the succession the match, reduces the possibility which the burr produces. Has three kind of situations in the power loss administration module to need to use the multi-channel selectors: a. Cuts the Normal pattern from the Slow pattern; b. Redeploys PLL under the Normal pattern; c. Cuts the Slow pattern from the Normal pattern. Figure 4 is in power loss administration module one two chooses MUX. Its control signal is OscillatorOrMPLL, two choice sources are clk_MPLL and clk_Osci, the output are out_ClockSource. When OscillatorOrMPLL is “1″, MUX selects clk_Osci; When OscillatorOrMPLL is “0″, MUX selects clk_MPLL. Before MUX choice any clock signal, clk_MPLL or clk_Osci must already stabilize down. Emphasizes, here stability was not refers to already transported the complete clock signal, but was transports the high level or the low level. Like this when the selection switch achieves their that side, accepts does not have the burr, and will produce the operation clock signal to entire SoC. Although in by now this kind of operation because descended fall the SoC frequency, but this is temporary (about 2~3 crystal oscillator clock cycle), therefore to the entire SoC performance’s influence is miniscule. Then the signal which selects (clk_MPLL or clk_Osci) only then starts to transport does not have the burr clock signal, thus sends out finally the clock signal has removed the burr. Figure 5 Figure 5 is the system cuts from the Slow pattern to the Normal pattern time the succession chart. Opens PLL through the disposition power loss administration module’s internal register, namely in_PLLStartOrStop signal, triggers the Slow2Normal_r signal by it, indicated that current is going to transit from the Slow pattern to the Normal pattern. Then, triggers Lock by this signal the Time counter to start to count (counting value in formula which gives by the PLL IP provider to determine), then first enables the crystal oscillator clock the signal to switch off, then projects on the multi-channel selectors MPLL that side. Finally, enables the PLL clock the signal to open, by now obtained was passes through the frequency multiplication the PLL clock. May see clearly from the succession chart, in the clock source cut’s process, the clock which will send out finally (out_ClockSource) the frequency will reduce down (probably will be very obviously crystal oscillator clock rate 1/3 or 1/2); But if crystal oscillator clock rate which chooses above 10MHz, will then have the influence to the entire SoC chip performance. As for the gating clock circuit, already many people did the very extensive research in this aspect, this article regarding this have no longer made excessively many explanation [7]. 5 conclusions This article proposed one kind of SoC chip low power loss management games. Its basic philosophy is, first considered from the overall situation, in satisfies the performance under the premise, dynamic disposes the SoC chip according to each kind using the environment the clock rate. Then, from considers the single module alone partially, through judges its current active status to decide whether to open its clock source. This low power loss management plan already applied section of SoC which designs in us chip - - Garfield. Arrange in order Power Compiler after Table 2 the power loss analysis, may see clearly: Under the Slow pattern’s power loss is only under the Normal pattern about power loss 17%, but is lower under the Sleep pattern’s power loss. Table 2 power loss analysis result
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Therefore, solves in the SoC dynamic power loss is reduces the entire SoC chip power loss the key. Behind this article mentioned the power loss is refers to the SoC chip the dynamic power loss.
