1 introduction
In recent years, the money, was specially the paper money is robbed the event to occur unceasingly, serious influence social order, also caused the bank to have the serious loss in the economy. If is robbed the money cannot circulate in the market, will suppress the bank from an aspect to rob event’s occurrence. And one kind of solution is records each bunch of paper money the number, the paper money number which will rob will be established a database. Provides one kind of paper money number automatic diagnosis installment in the circulation of money market, for example unifies with the automatic money counting machine, with is robbed the currency number identification data the number database to compare, once has the same number to appear, then may confirm that the present circulation the money for the money which robs, thus limits its circulation, simultaneously is also advantageous in robs case’s solving. Moreover, as a result of paper money number’s uniqueness, through the recognition paper money’s on number, may help the recognition false coin. Overseas has one kind to examine the paper money to send flag signals machine, may to the model paper money, for instance US dollar, the pound and so on carry on the automatic diagnosis and the number printing, this kind of equipment’s model recognition speed is 1/second. However did not have the automatic money counting machine supplementary number automatic diagnosis installment literature report.
The recent years, domestic also has some units to develop the development paper money number automatic diagnosis installment, for example the Nanjing University of Aeronautics and Astronautics has developed one kind based on monolithic integrated circuit’s paper money number recognition system [3], realizes paper money image gathering using array CCD, realizes the number localization and the recognition using the monolithic integrated circuit. Its subject matter is enhances the number with difficulty the recognition speed. The Harbin Industry University has developed one kind based on DSP paper money number recognition system [4], its recognition speed is 8/seconds, but this speed for in the PC machine on simulation result, the actual prototype has not realized. In addition, this system uses CIS (i.e. contact type linear image sensor) to obtain the paper money image signal, has the sensor attrition problem.
In view of the above situation, this article gives one kind based on the DSP paper money number recognition system, the use area array CCD camera gathering paper money number image, namely each second gathers 25 images, but present automatic money counting machine paper money speed for each second several about, thus may realize with automatic money counting machine’s coordinate use. This system is composed of following several parts: (1) realizes the paper money number image digitization using Philip Corporation specialized video frequency decoder SAA7113; (2) realizes digital paper money number image gathering and processing using TI Corporation’s digital signal processor TMS320VC5410; (3) completes overall system and the PC machine between correspondence using TI Corporation’s asynchronous serial interface chip TL16C550.
2 hardware design principle
Based on DSP paper money number recognition system’s principle of work: Paper money simulated video image which absorbs from the area array CCD camera, transforms after the specialized video frequency decoder into the digital image. The digital video signal stores DSP after image buffer FIFO the data space, takes the following pattern recognition the data origin. The video frequency decoder coseparation journey field synchronizing signal and the picture element clock reference signal, takes the image buffer module the control signal. In order to preserve and record the number, after the recognition paper money number data storage in fast twinkle memory FLASH, or according to needs to transmit through the asynchronous serial port for PC machine. Complex programmable logical component CPLD plays the overall situation logical control in the overall system and realizes the windowing processing role to the gathering paper money image. System’s gross structure diagram as shown in Figure 1.
3 image gathering module
3.1 video frequency decoding chip SAA7113 in system’s application
SAA7113 is one kind of high integration rate, and the support interlace, many kinds of data output form’s video frequency decoder, the built-in I2C contact surface has provided simply to the chip internal circuit’s control function. The control mainly includes to SAA7113 to inputs the simulated signal the pretreatment, the chromaticity and brightness control, the output data form and the outgoing picture synchronized signal selectivity control and so on.
Is mainly aims at the gradation image in the overall system to image recognition processing to carry on, in SAA7113 provides in many kinds of data output form, the RAW form the picture element grey level which the direct output and the picture element clock corresponds on 8 output base pins, this kind of data format will compare with other forms to gradation image gathering will be more direct.
SAA7113 output RTS0 and RTS1 are the multi-purpose multiplying base pins, reads in the different control word through antithetical couplet address register SA12, may two output base pin disposition for good synchronized, the frame synchronization, the odd and even field locking and so on different signal. Establishes in this system RTS0 as the good synchronized signal, RTS1 establishes as the field synchronizing signal, simultaneously SAA7113 also outputs picture element clock’s synchronization reference signal LLC.
Carries on the establishment through the I2C main line agreement to the SAA7113 each control register, causes it to satisfy the system request. Because the DSP chip is the processing component, its control is quite weak, the general I/O mouth are quite few, but the monolithic integrated circuit has the very good control function, therefore uses at89C51 monolithic integrated circuit for the SAA7113 initialization work to complete. AT89C51 the monolithic integrated circuit interior non-hardware I2C bus interface, establishes in this monolithic integrated circuit’s P1.0 mouth as serial data line SDA, P1.1 establishes as serial clock line SCL, through the software simulation I2C main line, carries on the initialization to video frequency decoder SAA7113, its hardware principle as shown in Figure 2.
3.2 use CPLD to realize for image windowing processing
Using picture element clock LLC2 and good synchronized signal HS solid present interception VHDL procedure:
process(LLC2, HS)
variable temp: std_logic_vector (10 downto 0);
begin
if (LLC2′event and LLC2=’1′) then
if (HS=’1′)? then? temp:=temp ‘1′;
if (temp>80 and temp<241)
then Href<=’1′;
else Href<=’0′;
end if; else Href<=’0′;
end if; end if;
end process;
From the SAA7113 output’s digital video image is the view picture image, but to distinguishes the useful picture size is 40×200, for reduction image data reserves and process load. Through adjusts between the CCD camera and automatic money counting machine’s position, the use video frequency decoder’s line, field synchronizing signal HS, VS and picture element clock reference signal LLC, uses the VHDL language, to is interested the image region to carry on windowing processing. Makes the law is specifically: Signal VS on the scene is the high period, carries on the counting to good signal HS, causes to be interested the image period field signal output to high, in other region its signal for low, like this obtains new field signal VREF. With field interception resembling, uses good signal HS and picture element clock LLC2, obtains recent good signal HREF. Like this has realized image windowing processing through two counters. This article gave has carried on windowing processing to the image the diagram, and has given the line of interception VHLD procedure, intercepted similarly to the row interception VHDL procedure with the line.
3.3 realize image gathering using DSP
On after SAA7113 electricity initialization, has been at the active status, its picture element clock reference signal LLC is 27MHz, for picture element clock’s two times, namely the picture element clock is 13.5MHz. If the such quick clock rate will carry on image gathering to present the data missing directly the phenomenon. This article used advanced left array FIFO to take the image buffer first, stored in first FIFO the image data, read in FIFO through DSP the image data, completed the image gathering. The CCD camera outputs the PAL system, the field repetition rate is the 50Hz video signal, its line interval is 64us, the field rate duration is 20ms. In this system Chinese Library size is 40×200 likely, may see the interception after the oscilloscope the field rate duration is 2.56ms, but the DSP read-write cycle is 10ns, needs the time through the DSP read-write procedure probably is about 3ms, connects with the automatic money counting machine, will have the sufficient time to realize image gathering.
Because FIFO has not selected patches or strips of land as worth saving for seed, to the FIFO control is mainly to its read-write signal effective control. FIFO writes effectively controls after the CPLD image interception good field synchronizing signal as well as the picture element clock signal. After FIFO finished an image data, the use half-full signal took DSP the signal of stop, stored through the interrupt servicing subroutine the image data DSP the data space to take recognition processing the data origin. Reads the control to FIFO through to map it DSP the I/O space to realize, to carry on discrimination use address wire A15 and A14 with other components participates in the decoding. When FIFO reads the signal for high, the data bus is the high-resistance condition, thus realizes the main line isolation.
4 DSP storage space design
The DSP chip as a result of its improvement’s Harvard structure, the processing speed is quick, the special DSP instruction and realizes each kind of digital signal processing algorithm characteristic fast, widely applies in each kind of imagery processing system. Selects TMS320VC5410 in this system to take the central processor, this chip’s read-write cycle is 10ns, has on the rich piece resources [2].
According to the paper money number picture size and the number recognition algorithm’s request, this system expanded piece of 64Kx16 RAM outside DSP, the 0×0000-0×3fff memory block maps DSP the procedure space, the 0×8000-0xffff memory block maps DSP the data space. Simultaneously outside expanded piece of 256Kx16 FLASH chip SST39VF400A, loads the characteristic according to the DSP system program, is the 0×8000-0xffff memory block maps DSP the FLASH address in the procedure downloading process the data space, maps DSP in program load’s process the procedure space, its space’s discrimination carries on the control through DSP general I/O mouth XF. The FLASH address is 0×0000-0×7fff and 0×10000-0×1ffff and the 0×20000-0×2ffff memory block maps DSP the procedure space, saves as the recognition number result’s record uses.
5 realize using TL16C550 with the PC machine between correspondence
In image gathering debugging and to number algorithm debugging, to examine the image effect, must present the image in PC machine. Because the TMS320VC5410 serial port is the synchronized serial port, but with the PC machine correspondence is actually asynchronous serial receiving and dispatching, this article used asynchronous serial transceiver TL16C550 to realize DSP and the PC machine between correspondence. TL16C550 is one kind which TI Corporation produces has the asynchronous serial communication function large scale integrated circuit, through to register choice input end A0, A1, a2 different disposition realizes to this component’s control.
Maps in this system it DSP I/O spatial 0×8000 the address, DSP address wire A2, A1, A0 and 550 register selectivity control pin A2, A1, A0 is connected, namely through is the 0×8000-0×8007 space carries on register’s visit to the DSP I/O space address. What in TL16C550 receive and transmission use is identical signal of stop INTRPT, through enables the different interrupt to the data receive and the transmission, realizes system and the PC machine between correspondence through the interrupt mode.
6 system’s software designs
Uses the manual compilation the assembly language procedure, although has carries out the speed quick merit, but will be specially distinguishes the algorithm with the assembly language write program the procedure will be quite time-consuming hard sledding [4]. In order to enhance the procedure development the efficiency, uses TMS320C54x the C language to carry on software development [5]. Overall system’s software flow chart as shown in Figure 6:
At present character recognition’s algorithm are many, has the background characteristic point law, the template matching law, the structural feature analysis judgment law, the neural network recognition algorithm and so on. The structural feature analysis judgment law embarks from the character structure itself, the examination number’s structural feature, has the quick sort characteristic, according to the system speed’s request, this article to the number image which gathered uses this kind of recognition algorithm to complete the paper money number the recognition.
7 concluding remark
This system through uses the TI Corporation’s digital signal processor to realize paper money number gathering, uses Altera Corporation’s complex programmable logical component CPLD to realize for the image interception, the image gathering effect is good. This system besides has the general imagery processing system’s function, especially qualify dynamic image’s processing, has the extremely high timeliness.
Reference:
1. TMS320C54X DSP Reference Set, Volume 1:CPU and Peripherals, Texas Instruments, http://www.ti.com, 1999
2. TMS320VC5410 Data book, Texas Instruments, http://www.ti.com, 2000
3. Liu Jianye and so on, the paper money number read-in recognition system’s monolithic integrated circuit realizes, industrial control computer, 2002,15(1),69-71
4. Zhang Qingfeng, based on DSP paper money number recognition system’s research, Harbin Industry University master’s degree paper, 2003
5. Liu Yicheng and so on, TMS320C54X DSP application programming and development, Beijing University of Aeronautics and Astronautics Publishing house, 2002
6. Zhang Yong and so on, C/C language hardware programming, Xidian University Publishing house, 2003
