Introduction
USB, the serial port, and the mouth is PC machine and the peripheral device carries on the communication the commonly used connection, but regarding the data quantity big image, if uses the serial RS-232 agreement to carry on the data acquisition, the speed cannot meet the requirements which image data gathering needs; But carries on the data acquisition with USB, although can satisfy needs the speed, but the request peripheral device must support the USB agreement, but the USB agreement and the commonly used project software’s connection is not popular, brings the difficulty to the use. Some users to use standard parallel mouth (SPP) to carry on the data acquisition, but SPP agreement 150kb/s transfer rate regarding image data gathering, appears too low similarly. Therefore, to gather the data quantity big image data, this article uses had high transmission speed enlargement mode parallel mouth agreement (EPP) and FPGA, realized carries on high speed data gathering to the OV7620CMOS image sensor, its maximum speed might achieve 2Mb/s.
Hardware circuit plan
Figure 1 is based on FPGA and the EPP technology to the OV7620CMOS image sensor’s high speed data gathering system principle diagram, it is mainly composed of three parts: OV7620 parameter disposition electric circuit, image sampling circuit as well as PC read data circuit.
OV7620 parameter disposition electric circuit
System after on electricity needs to pick the chip to CMOS to carry on the initialization likely, by determines the gathering image the windowing position, the window size and colored or the black and white working pattern and so on. These parameter’s disposition is the SCCB connection which provides through the OV7620 chip on carries on.
The SCCB connection is uses one kind simple, the bidirectional two-wire system’s synchronized serial main line I2C main line, the connection lead wire has SCL and SDA. Because 89C2051 does not have the standard I2C bus interface, may use the software routine to simulate the I2C main line, the OV7620 windowing position and the windowing size, black and white and the color pattern as well as the scanning way may establish through the corresponding register. These registers are may read/write, the concrete operations method is as follows: May select the method which the page writes, namely in writes in the register process to transmit first writes permission instruction OX42, then the transmission writes the data the goal register address, then for the data which must write. After finishing a register, CMOS will add automatically the register address one, the procedure might continue to write downward, but did not need once more entry address. Reads the register is the similar process, but the instruction changes OX43.
The I2C main line function realizes is completely dependence SCL, the SDA on-line level condition as well as between both’s mutual coordination realizes. In the I2C main line terms stipulated the condition is as follows:
Start succession: When SCL is the high level, SDA presents a drop along;
Transmission succession: After the start condition satisfies, SDA is the stable data condition, SCL produces a pulse, will transmit bit data;
Reply succession: When from machine receive to a complete data byte, in the main engine releases SDA in the situation, the main engine outputs a clock pulse for SCL, from machine pulls lowly SDA, by table reply;
Stop condition: When SCL is the high level, SDA presents a rise along, this condition may solve many machine competition problems, namely when two components talk, the third party inserts can terminate the former’s data communication, its main feature lies in various components each to judge main line’s condition.
The I2C main line’s start and stop condition as shown in Figure 2.
Image sampling circuit
Image resolution which in tunnel’s parallelism, the non-destructive inspection, the verticality measuring instrument often select for 320×320, can satisfy the pattern recognition basically with the black and white pattern to the image characteristic point request. Therefore this systematic sampling’s parameter is in the image resolution takes for 320×320, the black and white pattern, in the ZV image form carries on.
CMOS image chip ZV port form’s output wave shape as shown in Figure 3. In the chart VSYNC is the vertical field synchronizing signal, its drop along expressed that an image’s start (CMOS is according to row gathering image), HREF is the horizontal field synchronizing signal, its rise along expresses a row image data start. PCLK is the output data synchronized signal, Y is the gamma controller information. How following introduces FPGA to image sensor’s data sampling.
In order to carry on the speed match, between FPGA and PC has two handshake signals: READY and ACK. They are coordinated FPGA to the identical data storage chip read-write process. READY was FPGA informs the PC image data already to read off the signal; ACK was PC informs the FPGA data to read off the signal, both were the low level are effective.
In data sampling period, pulls high READY, expresses is gathering, by now FPGA according to OV7620 VSYNC, HREF, PCLK produced image MEM_WR (to write a letter number) and ADDRESS (address), reads OV7620 the data to the high speed buffer, when to the next VSYNC signal, expressed that a data already picked, then applies for the READY signal to the PC machine transmission, indicated that image gathering completes, if PC does not start the sampling next data for answering signal ACK, FPGA to put to the high speed buffer, and covers the original data; If PC responds, FPGA stop sampled data.
PC read data circuit
The PC read data is carries on through and the mouth EPP pattern. Reads succession as shown in Figure under the EPP pattern 4. In reads under the pattern, nWRITE (EPP writes a letter number) maintains the high level, when nDATASTB (EPP reads signal) changes is low, preparation read peripheral device data; After peripheral device data preparation, causes nWAIT (peripheral device busy symbol) is high, by now the PC procedure (EPP data port) carried out I/O to the base address 4 ports to read the operation (the nDATASTB signal); In reads the pulse nDATASTB signal the rise along, on PC read data bus data. The entire process is completes in a ISA cycle.
FPGA completes the succession like chart which realizes to the EPP agreement 5. PC does not stop inquires the READY signal to be whether effective, when is effective until READY, PC only then may read the image data, simultaneously sets at high ACK, indicated that PC is reading in the data buffer the image data. By now the FPGA stop gathering image (did not produce writes a letter number), FPGA examines PC to send out through EPP reads pulse (CPU_DS), produces high speed buffer MEM_RD (to read signal) and the address, reads a byte from the high speed buffer to put to and the mouth on, simultaneously transmits a BUSY signal to PC on, after PC at this moment, may read a byte data, completes the entire data read-write. In the read data process EPP port’s PC_WRITE (writes a letter number) to maintain for the high level.
Conclusion
FPGA to the CMOS high speed data gathering method, may turn the CMOS driving component through FPGA the way which may control, PC may to the storage medium carry on indirectly the addressing operation. Has realized CMOS signal high speed gathering processing in this system with PC and the mouth, according to the fore-mentioned software and hardware method manufacture’s system, the actual stable sampling speed has achieved 15 /s, this system has applied in the pipeline non-destructive inspection prototype, the effect is good. This signal gathering method may also in other many need high speed image data gathering the situation application.
Reference:
1. Hu Jun and so on, carries on the data acquisition with EPP, the data acquisition and processing, 1997(6).
2. Huang Yunxin and so on, based on EPP agreement data acquisition system, Optoelectronic Engineering, 2001(4).
3. Hou Boheng, VHDL hardware description language and digital logic electric circuit, Xidian University, 1999(9).
4. OmmVision Corp, Public OV7620 Datasheet, 2000(5).
Author synopsis:
Hao Yingji, the Xian University of Science and Technology Mechanical Engineering department, associate professor, is mainly engaged in the microcomputer examination and the control aspect research.
Figure 1 system principle diagram
Figure 2 I2C main line’s start and stop condition
Figure 3 OV7620 in ZV port form output succession
Figure 4 under the EPP pattern reads the succession
Figure 5 FPGA realizes the succession to the EPP agreement
