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Introduction

    Enhances and large scale integrated circuit’s rapidly expand unceasingly along with the people to the real-time signal processing request, obtained the fast development and the application as the digital signal processing core and the sign digital signal processor DSP chip. Not only it may widely apply in the communications system, the graph/imagery processing, the radar sound navigation and ranging, the medicine signal processing and so on real-time signal processing domain. Speaking of ADI Corporation, after 16-bit fixed-point ADSP21xx and 32-bit floating point ADSP21xxx series, the other day has promoted the TigerSHARC series new component. This article introduced that uses this series the ADSP-TS201S chip to realize an image gathering processing system’s design proposal.

System overall concept

    This system may complete the image gathering, processing and the demonstration, thus realizes the target identification and the track intelligence signal processing. This system is to the camera digit, simulates two group video data carry on gathering, after the processing, through the PCI main line on PC machine demonstrates. The overall system mainly by the video signal gathering module, the DSP imagery processing module, the PCI interface module three parts is composed (Figure 1).

Figure 1 image gathering processing system diagram

System’s each functional module circuit design

· video signal gathering module

    The camera provides two group video signals: A group simulated video, a group digital video.

    The simulated video signal adjusts, the enlargement after the clamp, the signal sends in a/D switch, passes through after again the FPGA lock saves, the video signal transmission for DSP1; After the video frequency sync split electric circuit, separates the simulated video by LM1881 the line, the field synchronizing signal, uses in controlling the video data to gather DSP1, with the aim of carrying on the imagery processing. The clamp adjusts, video frequency synchronizing circuit as shown in Figure 2. The simulated video after transports puts the input, indiscriminately allocates 3.3V the central electricity, adds to a/D input end. After A/D transforms the data enters the FPGA lock to save. Transports puts uses ADI Corporation’s AD8047AR, A/D switch to use ADI Corporation’s AD9050. AD9050 is 10 A/D switches, takes its high 8 to enter FPGA. Sampling clock 12MHz, is the same with the digital video signal. By FPGA to 48MHz clock four frequency division productions.

Figure 2 simulated video input conversion electric circuit

    Camera’s digital video signal is 14 pair of difference signals, after FPGA the difference signal conversion for the single end signal, and the lock saves the data. Each picture element 14, each 320×240.

    FPGA uses ALTERA Corporation’s CYCLONE series EP1C3T144C-6, the disposition chip uses EPC2LC20. EP1C3T144C-6 has the difference signal transfers the single end signal the special-purpose I/O mouth. The lock has FPGA the digit, simulates two group video signals to output on the DSP1 data bus according to the working pattern choice, reads in processing by DSP1, the data rate and the simulated video sampling speed, the digital video data rate is the same. The working pattern choice, the stop-go control introduces FPGA through PIC9054.

· DSP processor module

    The DSP processor array module is mainly composed the multi-DSP processor system by 4 piece of high speed high performance’s DSP processing chip ADSP-TS201S, the ADSP-TS201S performance is as follows:

The key property target is as follows:

Exterior port 1G byte each second; Chain street intersection (each) 1G byte each second

    In the DSP processor array module DSP1 is the video signal which uses for to reorganize collects, after and carries on the corresponding pretreatment, delivers following DSP the data distribution, carries on further processing.

    The DSP1 parallel mouth receives the FPGA output the video data, but must meet FLASH, completes the DSP load. DSP1 IRQ0, IRQ1 makes the video input separately the frame interrupt and a line of interrupt, receives FPGA. Its junction circuit following shown in Figure 3.

    FLASH selects AMD Corporation’s AM29LV017D, is the 2M x 8-Bit memory, may through DSP1 to the FLASH programming, probably guarantee when the FLASH read-write, FPGA data-out bus D0~D13 is high-resistance, otherwise, when the data channel moves, should also cause FLASH to output for high-resistance, therefore comes chip select FLASH with BMS.

Figure 3 DSP1 and FPGA, FLASH connection diagram

    In the DSP processor array module DSP2 and DSP3 are use for to realize in the imagery processing main algorithm. DSP2 and DSP3 use the chain street intersection and the DSP1 connection separately, receives the data which transmits by DSP1, DSP2 and DSP3 also separately use the chain street intersection to connect DSP4, will process the data transfer through the chain street intersection to give DSP4, carries on next step processing and the data ordering. Moreover, DSP2 and DSP3 also directly use the chain street intersection connection, realizes between DSP2 and the DSP3 channel, thus may conveniently disposes DSP2 and DSP3 the assembly line or the parallel processing pattern.

    In the DSP processor array module DSP4 receives the data which DSP2 and DSP3 transmit, after carrying on further processes, finally will process the data transmits through the data bus to twin port RAM, through PCI connection chip PCI9054, for the data transmission PC machine. This twin port RAM uses 3 piece of IDT70LV27 (32K x 16-Bit), composes 96K x 16-Bit way, guaranteed that one time finished one (320×240 a picture element, each picture element two bytes), when after DSP4 wrote all over an image data, had the interrupt to PC machine, requested that PC machine read the data, when after a PC machine read image data, should provide the corresponding reply, permitted DSP4 refurbishing pair of mouth RAM. DSP array machine interlinked circuit as shown in Figure 1, DSP4 with pair of mouth RAM connection as shown in Figure 4. DSP4 meets 3 piece of pair of mouth RAM, forms the connection with PCI9054. DSP4 FLAG0 takes through the PCI9054 output video frequency transmission handshake signal.

    The ADSP-TS201S array machine selects the chain street intersection interconnection method, established the data transmission in the main direction of data transfer to start the FLAG signal to have the interrupt to receiving end IRQ, so that better realized the succession match.

    DSP1 has introduced the work/closure choice (the FLAG1 input), the data pattern (digital/simulation) chooses by the DATA14 pin read-, may when a data starts inputs, reads in a data access pattern, hereafter might not the reprocessing.

Figure 4 DSP4 and pair of mouth RAM connection