As a result of the gain image’s tool or the method influence, causes the gain image to be unable to manifest the primitive image completely the complete information. Therefore, carries on the pretreatment to the image appears very important. The pretreatment goal improves the image data, suppresses the distortion which does not need or strengthens certain regarding the following processing quite important image characteristic.
Usually according to the pretreatment goal’s difference, converges the pretreatment technology the image intensification technology and the image division technology two kinds. Image contrast gradient processing is the spatial domain image intensification one method. Because the gamma controller scope narrow will cause the image the contrast gradient not to be ideal, the available contrast gradient enhancement technology will adjust the image grey level the dynamirange.
The imagery processing usually uses the software or DSP (digital signal processor) realizes. If realizes using the software, when movement will consume the many PC resources, when the algorithm will be more complex will consume the resources will be more, regarding the situation which needs to process high speed is not suitable; But if uses DSP to realize, will raise the parallel at the same time instruction execute speed definitely to enhance, the high command speed will possibly cause the system design complication, and will increase the power loss and the cost. New generation’s FPGA integrated CPU or the DSP essence, may carry on the software and hardware coordination design on piece of FPGA, to realize SOPC to provide the formidable hardware support. What this article introduced is uses the FPGA parallel processing and the computing power, take Altera FPGA Stratix EP1S40 as SOPC which systems control’s core realizes.
System hardware platform
Uses develops the platform based on PCI main line’s FPGA, structure as shown in Figure 1. On the board the main hardware source includes: PCI bridge, FPGA, SRAM and SDRAM and so on other peripheral devices.
Figure 1 develops the platform based on PCI main line’s FPGA
The PCI bridge uses the PCI9656 bridge joint chip to realize, uses for to connect the PCI main line and 32 /50MHz board level local bus; FPGA including 41 250 logical units, 14 DSP modules, 112 embedded multipliers, 4 enlargement mode PLL (phase-locked loop) and logical resources and so on 4 fast PLL; SDRAM uses for the stored image data. The Avalon main line module completes on the entire piece between the programmable system module’s interconnection. The Avalon main line is in the SOPC design continually on the contact tag the processor and other IP module one kind of simple main line agreement, had stipulated main, from component’s port connection as well as the correspondence succession relations, SOPC Builder completes the overall system (including Avalon) the module production and the integration. The rich board level resources may satisfy the image the high speed pretreatment demand.
System principle of work
The design uses the DMA way speedy transmission image data, such data’s transmission and processing may parallel, causes system’s operating efficiency is the enhancement greatly. PC and between the PCI board card establishes the software environment, under this environment using the DMA channel the image data from the main engine through the PCI main line, the PCI bridge, the board level local bus and the Avalon main line passes to SDRAM to save, then sends in the algorithmic logic module to carry on processing, after processing completes, the image data saves again to SDRAM, finally uses the DMA channel again the imagery processing readout main engine.
Establishes on the piece in system’s essential module
This article designs the image contrast gradient enhancement system is the establishment in Stratix EP1S40 foundation SOPC. This design II in 5.0 the systematic operating frequency will suppose in Quartus using SOPC Builder will be 50MHz, the component series supposes is Stratix, the IP module which and the algorithmic logic module the transfer already established, and establishes each module the clock and the base address, the disposition lives on the Large expanse of system. According to the mission requirement, SOPC structure diagram as shown in Figure 2.
Figure 2 SOPC structure diagram
In Figure 2, the Avalon bus interface divides into advocates (Master) and from the (Slave) two kinds, the former has the docking Avalon main line’s domination, the latter is passive. From has custom-made Avalon divides into two kinds differently from the peripheral device basis to the Avalon main line operating mode: One kind is Avalon from the (Slave) peripheral device, is only processes as Avalon main line’s one from the part; Another kind is the Avalon class pattern from (Streaming Slave) the peripheral device, needs to use the Avalon main line’s class mode of transmission, the peripheral device design is more complex.
* board level local bus and between Avalon main line bridge’s connection module
Main line bridge establish the connection module in the board level local bus and FPGA between the internal Avalon. Because between the SOPC interior various modules’ logical link is completes by the Avalon main line, therefore may visits the SOPC module from the main engine through the PCI main line and the board level local bus. This module takes a Avalon main line’s master control connection, carries on the visit and the control to other Avalon from the peripheral device and the Avalon class pattern from the peripheral device.
* control module
Control module’s work clock independence in the system clock, as shown in Figure 3. Including two module designs: (1) uses to the SDRAM memory resources makes the rational distribution the class pattern memory supervisor module, it takes the Avalon class pattern from the peripheral device, read-write port’s quantity may dispose, these read-write port may or reads in by the class mode of transmission the image data read-out SDRAM. (2) memory control module, it takes Avalon main line’s another master control connection, to from controls the connection as the Avalon main line the SDRAM controller to carry on the control.
Figure 3 control module
* the image contrast gradient enhancement algorithm and VHDL realize
In the image contrast gradient processing method, may design the different transfer function. This system is aims at the zigzag function transformation design, the zigzag transforms may stretch several section of narrow gradation sectors to the wide density latitude, this kind of processing may the gradation change gentle region also distinctively demonstrate that thus in the enhancement image is interested the characteristic.
This design to a 3008×2000 picture element, the data width is 8 gradation images carries on processing, the image altogether has 2000 line, 3008 row picture element spots, line and the row from 0 start to count. When the system clock rises along, a line of desired signal and the data desired signal is effective, the image data reads, makes corresponding processing to it. Each system clock rises along reads in an image data, after the Nth line of picture element spot processes, a N 1 line of desired signal and the data desired signal must be simultaneously effective can continue to process, in after 1999th line, 3007 row picture element processing finished, a line of desired signal and the data desired signal set to invalid, this time the entire frame imagery processing finished. In the algorithmic logic module needs the frame effective counter and line of effective counter each, uses for separately to the frame and the line carries on the counting, but also needs a picture element counter to make the counting statistics to some line of picture elements. Because this algorithmic logic module is based on the SOPC technology, can tool take in SOPC in the Builder from has custom-made the module to transfer, must establish two registers, respectively is the frame effective counter register and the line of effective counter register, they act according to the Avalon main line address the difference, simultaneously reads or writes the register as the Avalon main line, thus causes may carry on the correspondence from the definition module with the Avalon main line. Which sector scope inputs a picture element spot to judge its grey level every time to satisfy the establishment and makes the corresponding transformation, thus realizes an image contrast gradient enhancement processing. According to the algorithm demand, uses the VHDL language to the algorithmic logic modelling, and transfers by the Avalon main line from the peripheral device way in SOPC Builder. VHDL realizes as follows.
entity enhancement is
port (iLVAL: in std_logic;
iDVAL: in std_logic;
iFVAL: in std_logic: = ‘1′;
iCLK: in std_logic;
iDATA: in std_logic_vector (7 downto 0);
oLVAL: out std_logic; oDVAL: out std_logic;
oFVAL: out std_logic;
oDATA: out std_logic_vector (7 downto 0)
);
end enhancement;
Here iFVAL is set at is “1″, showing is carries on processing to an image; iDATA and oDATA are the image input, the output binary system data, the width are 8.
Image pretreatment system’s realization
Establishes the FPGA module with standardized hardware description language VHDL to realize. Produces each design social stratum according to the design method from the top, the task of design will decompose into the different functional element, each part has specially the definition input/output port and carries out the respective logical function. This SOPC design realizes through the below step.
(1) tool translation production user from has custom-made the module using SOPC the Builder, the transfer already the IP module which establishes and establishes the parameter, the disposition lives on the Large expanse of system;
(2) in the top layer VHDL document calling module and demonstration, clear signal connection;
(3) pair of overall system carries on restraint establishments and so on base pin, all translates and carries on the behavior and the succession confirmation;
(4) downloading and the hardware debug complete.
Concluding remark
This system a 3008×2000 gradation image which pats in the optical fiber weak situation carries on contrast gradient enhancement processing to the laboratory, around processing like Figure 4, 5 shows. When the SOPC system clock is 50MHz, regarding input size for 3008×2000 picture element gradation image, each process time for T=(1/(50×106))×3008×2000=0.120 32s.
Figure 4 original image
Figure 5 after the processing, image
But on 3GHz Pentium 4, 256MB memory PC through Matlab with the code realizes, then needs 0.9850s. This design uses FPGA to realize the image pretreatment system, with compares using the software processing image’s method, may realize fast to the image pretreatment. Simultaneously the system constitution is flexible, in the design the module might duplicate the growth oriented to reduce the production cost, to reduce the production cycle, raised the working efficiency.
