between 1 board shared buffer memory’s hardware interface electric circuit and software control flow
1.1 signal processing board hardware interface electric circuit
May act according to based on the DSP signal processing board using the request moves many signal processing algorithm, like signal pretreatment, target identification and track localization, Kalman filter and so on. Waits processing the primary signal data to correspond through the board between the data acquisition board obtains. Here uses between the board shared buffer memory’s method to complete the data exchange, DSP already may from the shared buffer memory read gathering data, may also the processing result (for example new program control enlargement factor value, track localization result and so on) write in the shared buffer memory to read for MCU.
TMS320C32 has a bidirectional serial port, may establish each simultaneously to receive and dispatch 8/16/24/32 bit data, the synchronized clock may produce by the internal serial port timer or by the external input. Controls the serial port through the establishment serial port overall situation control register the overall function and the working pattern; Through establishes the FSX/DX/CLKX port control register and the FSR/DR/CLKR port control register controls the serial port 6 pins the functions, may the software establish each pin as the general I/O pin or the serial port correspondence pin. TMS320C32 has two general I/O pins is XF0 and XF1, because the shared buffer memory interface circuit needs 4 pilot wires to carry on DSP and the MCU handshake correspondence, here establishes serial port 2 pin FSR0 and FSX0 for the general I/O pin serves as the pilot wire. Interface circuit schematic diagram as shown in Figure 1.
In the chart RAM0~RAM3 is four piece of capacities is 512K 8 high speed RAM (chip model is CY7C1049-17VC), composes 32 bit data widths the memory, time the DSP movement procedure and the data in these four piece of RAM. FLASH (chip model is Am29F016) uses in the stored routine and the initialization data, even if the power failure content does not lose, on DSP when electricity procedure takes out the procedure from bringing BOOT the LOADER from FLASH to move to four piece of RAM. Also temporarily stores from the shared buffer memory read’s gathering data to these four piece of RAM.
1.2 data acquisition board hardware interface electric circuit
Based on the monolithic integrated circuit AT89C51 data acquisition board under monolithic integrated circuit’s overall situation control, through the weak signal which outputs to the multi-channel sensors carries on the program control to enlarge, the low-pass filtering, the synchronized sampling maintains, a/D transformation, the real-time synchronized gathering multi-channel signals, and the signal data which gathers deposit on the data acquisition board the 128K shared buffer memory (chip model are CY7C109-12VC).
Shared buffer memory and main line isolating circuit design on data acquisition board. In one time, the shared buffer memory can only by some side visit, will otherwise have the main line conflict. Here selects the DSP main line or the monolithic integrated circuit main line by the MCU cut, time sharing visit shared buffer memory. The main line isolation chip selects common bidirectional bus isolation/actuation chip 74HC245, it has an output to enable pin (E) and a direction of data transfer (DIR) pin, MCU through controls these two pins to complete the main line isolation and the direction of data transfer control function. Interface circuit schematic diagram as shown in Figure 2. In the chart, the MCU end’s main line isolation completes by piece of 74HC373 and two piece of 74HC245, DSP origin three piece of 74HC245 completes the data bus and address bus’s isolation. Selects which group of main lines by the P1.2 control, when P1.2 is the low level, the shared buffer memory can only by the MCU visit; When P1.2 is the high level, only then, when P1.3 also for high level (expressed that MCU agreed resigns shared buffer memory), the shared buffer memory can by the DSP visit. Because DSP needs to read or to write the shared buffer memory, therefore needs software establishment data bus isolation chip 74HC245 the direction of data transfer, here through establishes the DSPDIR holding wire’s level condition completes (when high level to read, when low level to write). Because address bus’s direction of data transfer is throughout unidirectional, therefore its isolation chip’s DIR end may meet the low level or the high level fixedly, regards 74HC245 the actual wiring to decide.
1.3 software control flow
On signal processing board’s DSP needs to gather when the signal data sends out the request signal to data acquisition board’s on MCU, after the monolithic integrated circuit receives the request signal, if agreed that resigns the shared buffer memory, sends out the answering signal to DSP, simultaneously isolates the MCU end the main line, suspends the data acquisition. After DSP receives the answering signal, may visit the shared buffer memory, after the DSP quick speed reading, finished the data, to the monolithic integrated circuit sends the conclusion signal, after the monolithic integrated circuit received the conclusion signal, the reclamation shared buffer memory, simultaneously isolates the DSP end main line, continued to gather. Such data acquisition and the signal processing may also carry on, are different process a part of serial working pattern in a general gathering section, realized data acquisition zero to wait for, increased system’s handling capacity. See also Figure 3 wiring diagram, a complete course of communications specification is as follows, pays attention when the DSP procedure initialization should XF0, XF1, FSR0 establish as the corresponding invalid condition.
1 燚 SP needs to gather when the signal data sends the request signal to MCU (to set at XF0 is low level), triggers MCU the INT0 interrupt, waits for the MCU reply (DSP the loop check XF1 condition).
2 犎 quan 鸐 CU agreed that resigns the shared buffer memory, then response interrupt, otherwise waited. In the interrupt service, sets at P1.3 (i.e. DSPACK) is the high level, expresses the reply. Simultaneously sets at P1.2 is the high level, selects the DSP main line. MCU then loop check P1.4 熂 碊 SPEOR) condition.
3 燚 SP receives the answering signal (i.e. to examine XF1 is high level), is fast immediately the read-write shared buffer memory, before reading the operation, sets at FSX0 is the high level, before writing the operation, sets at FSX0 is the low level. After read-write, sent the conclusion signal to MCU (to set at FSR0 is high level), DSP followed closely is carrying on other processing operation.
after 4 燤 CU received the conclusion signal, (i.e. examined P1.4 is high level), set at P1.2 is the high level, isolated the DSP main line, the reclamation shared buffer memory, continued to gather.
2 signal processing board and control > system’s correspondence
Signal processing board after data acquisition board gain gathering data, passes through carries on a series of signal processing algorithm to it operation processing, obtains the processing result needs to transmit for based on the monolithic integrated circuit or microcomputer’s control system. Because here processing result data quantity is very small, therefore carries on the data transmission using the serial port correspondence’s method to be simplest. We may the DSP serial port program directly to the signal processing board on carry on the correspondence with the control system. But because the DSP serial port is the synchronized serial port, but the monolithic integrated circuit or microcomputer’s serial port usually is the asynchronous serial port, like this needs to use the software to simulate the DSP serial port the asynchronous communication succession, the software work load moreover the correspondence is greatly unreliable. Here through expanded the monolithic integrated circuit and shared buffer memory’s method has solved this problem well. DSP writes about the processing result in the shared buffer memory, carries on next round processing immediately, takes out the processing result by the monolithic integrated circuit from the shared buffer memory and transmits for the control system. This omitted DSP to carry on the time which the serial port message center needed, maximum limit has used the DSP high speed data processing ability. In the timely request very high situation, this appears especially important. Through expansion few hardware, not only raised system’s speed, optimized the overall performance, moreover the software realized simply also many.
2.1 signal processing board and control system’s serial port correspondence hardware circuit
The signal processing board use expands monolithic integrated circuit AT89C51 with carries on the full-duplex based on the microcomputer or the MCU control system to correspond. Figure 4 is at89C51 serial port communication circuit, adopts ” the serial port choice ” to dial the code switch choice is and based on microcomputer’s control system correspondence, with based on MCU control system correspondence.
In IBM in the PC/XT microcomputer system, its serial port conforms to the RS-232C interface standard. In order to sharpen the antijamming ability, the RS-232C standard uses negative logic, the low level between - 5V~-15V (usually with - the 12V expression) is logic ” 1 “, the high level between 5V~ 15V (usually with the 12V expression) is logic ” 0 “, the above level is called the EIA level, it and the TTL level and the CMOS level are different. In order to enable AT89C51 to carry on the serial communication with the microcomputer, may use common MC1488 and MC1489 carries on the level switch. MC1488 the TTL level switch is the RS-232C level, MC1489 the RS-232C level switch is the TTL level. But because MC1488 and MC1489 need ±12V the power line voltage, increased power circuit’s complexity, as shown in Figure 4, here selects only needs sole 5V voltage MAX232 to complete the level switch, simplified the hardware circuit.
When signal processing board with based on MCU control system correspondence, only needs three lines, transmission line (TXD), meets recover of wire (RXD), altogether grounding (GND), the bilateral grounding continually in the same place, with meets the bilateral transmission line the recover of wire cross connection then. When signal processing board with based on microcomputer’s control system correspondence, carries on the correspondence using microcomputer’s nine needle serial port, their serial port cable segment as shown in Figure 5. Here transmission line with meets the recover of wire not overlapping, is because when carried on the level switch already intersected (had see also Figure 4).
2.2 signal processing board and control system’s serial port correspondence software programming
The monolithic integrated circuit and the monolithic integrated circuit or the microcomputer carry on the serial port correspondence the software programming to have two kinds: Inquiry way and interrupt mode. Here transmitting end (signal processing board) selects the inquiry method, the receiving end (control system) uses the interrupt mode. The signal procedure mainly completes to the serial port initialization (including choice serial port pattern, establishment data transmission form, establishment baudrate and so on), functions and so on establishment connection, transmission data and separation connection. In order to guarantee the correspondence to be reliable, both sides agree the following communication protocol.
1st, on after signal processing board electricity, has transmitted the request on-line signal ‘ the R’, waiting control system to send the answering signal ‘ A’, if the signal processing board receives the reply, indicated that the bilateral hardware connection is correct, on-line success.
2nd, operating control system’s serial port signal procedure. If with microcomputer correspondence, what then first automatic detection connection is which serial port (COM1 or COM2), after examining, sends the answering signal to the signal processing board ‘ A’;, if has not examined, then demonstrates the error message, prompts the inspection wiring whether to contain errors. If with monolithic integrated circuit correspondence, if (for example in 10s) has not received the reply in the stipulation time, lets the indicating lamp glitter, thinks makes a mistake, must reposition.
3rd, after the signal processing board receives the reply, first data integer which altogether must transmit to the control system transmission, then transmits each data in turn, until sends.
4th, after the control system sends on-line answering signal, is at the accepting state. Receives altogether data integer first, then receives each data in turn. The control system receives every time to a data sends the confirmation signal to the signal processing board, after the signal processing board only then receives the confirmation signal, only then distributes a data.
Moreover, carries on the correspondence when the monolithic integrated circuit and the microcomputer, both sides must correctly choose the consistent baudrate 煻, and SMOD position choice influence monolithic integrated circuit baudrate accuracy, namely influence baudrate error range. Therefore when monolithic integrated circuit baudrate establishment, also wants the due consideration to the SMOD selection. In order to guarantee that the correspondence the reliability, usually the baudrate relative error do not be bigger than 2.5%, when between the monolithic integrated circuit and the microcomputer carries on the correspondence, especially must pay attention to this point. For example, monolithic integrated circuit’s clock fOSC=12MHz, the serial port pattern for the way 1, the supposition monolithic integrated circuit and microcomputer’s baudrate elects is 9600bps. When SMOD=0, the baudrate relative error is 8.5%, when SMOD=1, the baudrate relative error is 6.99%. The experiment indicated that no matter SMOD=0 or 1, the monolithic integrated circuit and the microcomputer cannot realize the normal transmission and the receive under this kind of condition. If the bilateral baudrate takes 4800bps, and time SMOD=1, the baudrate relative error is 0.16%, the experiment proved that the correspondence is completely reliable.
Reference
1 Texas Instrument.TMS320C3x User’s Guide.USA:Texas Instruments Incorporated,1998
2 Maxim Corporation.±15kV ESD-Protected 煟 5V RS-232 Transceivers. USA:Maxim Integrated Products,1996
3 Wang Furui. Monolithic microcomputer observation system design comprehensive work. Beijing: Beijing University of Aeronautics and Astronautics Publishing house, 1998
4 Li Hua .MCS-51 series monolithic integrated circuit practical connection technology. Beijing: Beijing University of Aeronautics and Astronautics Publishing house, 1993
