Abstract: This article introduced based on PCI main line’s DSP digital signal processing board hardware architecture, and concrete discussion it in design application method.
Key word: PCI main line, DSP, PCI9054.
Introduction
PCI main line standard which promotes primarily by INTEL Corporation. Uses the disposition space which as well as the PCI main line the PCI main line equipment has through the bridge circuit and the CPU connected technology enables the PCI main line to have the widespread compatibility, simultaneously can satisfy high-speed equipment’s request.
On the other hand, the DSP development exceptionally is also rapid. ADI Corporation had issued in 2001 its high performance TigerSHARC the series DSP young blood, uses such series the chip, may develop the handling ability to be stronger, the volume is smaller, the development cost is lower, performance-to-price ratio higher signal processor. And widely applies in the signal processing, the correspondence, the pronunciation, the image and the military and so on each domain.
TS101S introduced
This system uses American ADI Corporation’s high performance TigerSHARC 101S to take the main processor, is called TS101S. ADSP the TS101S processing supports 32bit and the 64bit floating point, as well as 8, 16, 32 and 64bit fixed point processing. Its static excess structure enables DSP every week the time to carry out reaches 4 instructions much, carries on 24 16bit fixed-point arithmetic and 6 floating point calculations. Its interior has three mutual independent 128bit widths and the internal data main line, each strip connects in three 2Mbit interior memory block’s one, provides 4 characters the data, the instruction and the I/O visit and the 14.4Gbyte/S internal memory bandwidth. Moves when by the 300MHZ clock, its essence instruction cycle is 3.3ns. After displaying its single instruction multi-data characteristic, ADSP TS101S may provide each second 2,400,000,000 40bitMAC operation or 600,000,000 80bitMAC operations. Moves when by the 300MHz clock, completes 1024 plural number FFT (base 2) time only 32.78us. 1024 input 50 tap FIR to need 91.67us.
ADSP TS101S has the formidable link to transmit orally loses the function, each link transmits orally loses the speed to achieve 250Mbyte/S. The total link data rate reaches 1Gbyte/S (4 chain street intersections), had already surpassed exterior the mouth transmission speed (800Mbyte/S).
Signal processor’s hardware architecture
The system structure mainly includes A/D to transform, the data storage, the logical control, the clock assignment and the data transmission five big modules. As the core processing unit signal processor is inserts the card take DSP by PCI in the form straight insertion computer’s PCI main line slot. The signal processor through the PCI connection chip and the PCI bus interfacing, its function is realizes between PC machine and the signal processor the data transmission and the memory. Its system structure drawing like chart 1:
Figure 1 system structure drawing
And a/D switch uses AD Corporation 16 high accuracy A/D chip AD976ARS, it is uses the electric charge heavy distribution technology to approach the mold number switch gradually, the structure approaches ADC the tradition to be simpler than, and no longer needs the complete modulus switch to take the core. AD976ARS has the following characteristic:
* it is 16 high accuracy A/D, may achieve 16 not to lose the code.
* has the high speed parallel interface.
* the conversion rate is 200ksps.
* may choose the interior or the exterior 2.5V reference supply.
* has on the piece the clock.
May receive/and transport directly puts the AD8033 output, AD8033 is the low power loss, the high accuracy transports puts, here meets the follower pattern. Transforms the clock to give (R/C) signal by CPLD, CPLD switches over DSP1 TMR0E, after and but actually, forms the R/C signal, like this, data acquisition’s cycle by the DSP timer control, may realize the cycle adjustable. Also introduces the AD976AARS BUSY signal CPLD, uses in the lock saving a/D transformation data. Transports puts with a/D circuit structure like chart 2:
The system uses 1 piece of CPLD (EMP3256) to make a/D transformation data-in lock to save, to produce the reset signal which DSP needs and so on. At the same time, CPLD must complete the PCI bridge’s some control signal production, the transfer. In fact is also takes the PCI local bus’s arbitration, it proposes to the PCI connection chip and DSP takes local bus’s request to carry on the arbitration, is coordinated between them the logical relation, causes on local bus’s operation to carry on smoothly. The system also used two 16K×16 position pair of mouth RAM IDT70V261 to constitute the DSP signal processor and the PCI connection, RAM1 made the data feeds, RAM2 made the data output.
The PCI bridge uses PCI 9054 to complete, PCI 9054 are PLX the Technology Corporation’s new product, is a low cost, the low power loss, the function strong PCI bridge chip, may connect the PC machine PCI main line and the local bus, is advanced PCI the I/O accelerator, has used the advanced PLX data assembly line structure technology, is 32, the 33MHz PCI main lines advocates the I/O accelerator; Conforms to the PCI local main line standard 2.2 editions, has M, C, the J three kind of patterns; May elect in view of the different processor and the bureau main line characteristic, reduces the middle logic as far as possible; Has the serial E2PROM connection which may elect, the local main line clock may with the PCI clock asynchronous. The PC9054 interior has 6 kind of programmable FIFO, realizes between the zero waiting burst transmission and the local main line and the PCI main line’s asynchronous operation; Supports principal-mode -like, from the pattern, the DMA transmission mode, because its formidable function may apply in the adaptive card and the embedded system. But because DSP has not provided directly with the PCI 9054 connection pins, therefore uses pair of mouth RAM to make the data buffering, its merit does not need to transform PCI to produce the signal to adapt the DSP request. The succession disposes is easier. At the same time, separates the establishment the output input channel, also has facilitated user’s application.
DSP1 and EPROM, double mouth RAM, and CPLD connection like chart 3:
Double mouth RAM uses IDT70261, it is high speed 16kX16 which produces by American IDT Corporation has interrupt twin port SRAM. It uses the 100-pmTQFP seal, the typical power loss is 750mW, the biggest access time has two ranks: The commercial level has 15/20/25/35/55ns(max), the technical grade has 20/25/35/55ns(max). It has the following characteristic:
(1) has two sets of completely independent pilot wires, the address wire and the I/O line, allows at the same time two independent systems to carry on visit to the twin port memory.
(2) has the completely independent busy logic, may guarantee that two systems carry on the read-write operation to the identical unit the accuracy. (3) interrupt logic allows CPU to carry on the correspondence directly through the port, marker logic permits two controller shared resource.
(4) permission data zero access, the minimum access time is 15ns, may with the majority high speed processor coordination use, not need to insert the waiting status.
(5) has the Master/Slaver control foot, can expand conveniently on the storage capacity and the data bit wide.
(6) various ports completely asynchronous operation.
Double mouth RAM makes DSP3 (TS 101S) to output the interim, therefore and DSP3 WRL is connected. DSP3 and pair of mouth RAM connection like chart 4: 
This system uses between the DSP piece by the chain street intersection interconnection way, retains 2 link channels every time to DSP, the total data rate may reach 500Mbyte/S. Uses the chain street intersection interconnection to be possible to simplify the PCB board greatly the order of complexity. The chain street intersection interconnection is the ADSP series chip unique function, is also the ADSP processor can compose the many piece of high performance signal processor’s primary factor by the low cost. DSP connection like chart 5:
Concluding remark
Of this system uses from exterior gathering signal, makes the signal processing after the digital signal processor’s on DSP chip, then realizes with the PC machine live transmission and the data storage, therefore may carry on the real-time renewal to the signal processing result, thus realizes high speed data transmission between the digital signal processor and the corresponding equipment’s. This system may also apply in the high speed data gathering card, the video frequency transaction card, the network card and so on the high-speed equipment. And TigerSHARC series chip by its formidable operational capability, thus big reduced the development cost, simultaneously signal processor’s development cycle may also be the reduction greatly, easier development performance-to-price ratio higher signal processor. But PCI 9054 take its formidable function and the simple user interface, as the PCI bus interface development has provided one succinct method, this system after the test, the high speed data could gather and the transmission correctly. In the high speed data transmission system, uses the PCI main line’s high-speed characteristic live transmission and the memory gathering data, the effective addressing data’s transmission and processing timeliness, along with the PCI main line’s popularization application, had the very broad prospect based on the PCI main line’s transmission system design.
Reference
[1] Soviet Tao, Cai Jianlong, He Xuehui the .DSP interface circuit designs and programs Xi’an: Xidian University Publishing house [2] Liu Shuming, Soviet Tao, Luo Jun splendor .TigerSHARC the DSP application system designs Beijing: Electronics industry publishing house, 2003.
[3] ADSP-TS101 TigerSHARC Processor Hardware Reference.
