Introduction
Along with the new generation battle airplane massive equipments active duty, airborne radar set’s repair task is getting more and more arduous, the modernized simulation test system becomes the important maintenance equipment. Radar signal’s simulation is also in the test system essential. But uses the function/random wave generating apparatus composition test system, not only increases the system cost, moreover gives back to the system software design to increase the nonessential burden. Therefore, proposed one kind realizes the plan based on the CPLD radar simulation signal, it can provide many kinds of model repetition frequency pulses which and the homing signal for the airborne radar approach test system needs.
Radar simulation signal generating device structure
The radar simulation signal generating device mainly and produces the simulation signal CPLD chip two parts by the input output control to be composed. The input output control signal is controls using test system’s labor machine produces through the digital I/O card, when the labor controls machine through the digital I/O card output desired signal, the generator will output the corresponding signal impulse. Radar simulation signal generating device’s structure as shown in Figure 1.
Figure 1 radar simulation signal generating device structure
In the chart, the radar simulation signal generating device’s control signal has the radar simulation signal pulse switch, the union signal UNITED switch, the homing signal SA-H switch, the homing signal SA-L switch and the illumination outputs the SA-W switch. The above switch is the low level is effective, when “the pulse switch” is effective, the radar simulation signal generating device namely is at the active status. By now any control signal effective so long as could cause its output corresponding radar simulation signal. When “SA-H” is effective, “out1″ outputs the high repetition frequency signal impulse; When “SA-L” is effective, “out1″ in output repetition frequency signal impulse; When “SA-W” is effective, “out2″ output illumination signal impulse; When “UNITED” is effective, “out3″ output union signal impulse, namely when illumination pulse bottom level joins the high repetition frequency or the repetition frequency signal impulse.
CPLD internal circuit design and simulation
In this design selects CPLD is Altera Corporation’s EPM7128SLC84, belongs to the MAX7000 series. The MAX7000 series provides 600~5000 available (on component to provide 1200~10000), the pin to the pin time delay is 6ns, the counter frequency may reach 151.5MHz.
CPLD is the radar simulation signal generating device core is, its internal circuit mainly divides into 6 sub-modules, respectively is 5 frequency divisions and the pulse width reshaping module, 10 frequency divisions and the pulse width reshaping module, 60 frequency divisions and the pulse width reshaping module, 100 frequency dividing circuits, 625 frequency dividing circuits and the pulse output selectors. Between various modules connects relations as shown in Figure 2.
Figure 2 between CPLD interior various modules connects the relations
The clock pulse inputs the CLK frequency the 10MHz signal which provides for the exterior crystal oscillator, is 10 frequency divisions and the pulse width waveshaping circuit, 60 frequency divisions and the pulse width waveshaping circuit, 100 frequency dividing circuits provides the 50ns pulse width the input signal. 100 frequency divisions and 625 frequency dividing circuits use MAX PLUSⅡBrings great function LPM-COUNTER (to be possible preset counter) to design, 10MHz signal by LPM-COUNTER clk end input, but after cout takes the frequency division the pulse out-port, according to the pulse frequency which needs establishes function modulus and the width parameter, take 100 frequency dividing circuits as the example, the modulus establishment is 100 corresponding width establishments is 7, when the great function each control signal establishes after to count the condition, when the clk rise along arriving at starts to count. When counts to 100, the clear and outputs a pulse width in cout is the clk clock cycle pulse, so relapse, thus achieves 100 frequency divisions the goals, Figure 3 gives 100 frequency divisions the simulation profiles.
Figure 3 100 frequency division simulation profile
60 frequency divisions and the pulse width waveshaping circuit have the cycle 6μs, the pulse width 1.2μs high repetition frequency pulse, its structure as shown in Figure 4. The frequency dividing circuit uses the above similar design method, only need modulus and the width parameter distinction establishment be 60 and 6, namely has the cycle for 6μs the pulse width 100ns pulse (Figure 5 clk100ns). Takes the D trigger’s clock signal this signal, but this D trigger’s input end maintains the high level throughout, when like this D trigger in the clock rises after the arrival the output will maintain throughout “1″, but to obtain 1.2μs the pulse width pulse will probably after 1.2μs to the D trigger reset. The reset signal’s design uses the LPM-COUNTER function, the function input signal is similarly the 10MHz signal impulse, modulus and the width parameter distinction establishment is 13 and 4, when counts to 13 (the clk input end presents the 13th rise along, namely clock past 12 cycles 1.2μs) clear and, in cout produces the pulse to meet the D trigger through the phase reverser (Figure 5 D:CLRN) to reset the end to cause its output to the trigger reset “0″. In order to cause the counter when the D trigger outputs “0″ is not at the counting condition, turns on LPM-COUNTER the D trigger’s out-port through the phase reverser the synchronized reset to carry aclr. This then can, in the D trigger out-port obtains the needing high repetition frequency signal (Figure 5 f166k), Figure 5 has given its simulation profile.
Figure 4 60 frequency divisions and pulse width reshaping structure drawing
Figure 5 high repetition frequency signal simulation profile
10 frequency divisions and the pulse width waveshaping circuit have the cycle 60μs, the pulse width 3μs repetition frequency pulse. Its design uses with the high repetition frequency signal same method, is only takes the high repetition frequency signal its 10 frequency dividing circuit’s input.
5 frequency divisions and the pulse width waveshaping circuit produce cyclical 50ms, the pulse width 31.25ms illumination pulse. It mainly by a LPM-COUNTER function and the decoder 74138 constitutions, the LPM-COUNTER clock input uses cyclical 6.25ms which, the pulse width 10us pulse 100 frequency divisions and 625 frequency divisions produce (to see Figure 2). LPM-COUNTER the function width parameter establishment is 3, its q [2..0] output 0~7, takes it as decoder’s input, by now will maintain separately in decoder’s 8 out-port y0~y7 6.25ms “0″. Takes the input y0~y4, may obtain the 31.25ms pulse width to 5 input AND gates. But the decoder 8 clock cycle’s circulation constitutes the 50ms repetition interval. Figure 6 is the illumination pulse simulation profile.
Figure 6 illumination pulse simulation profile
Outputs the selector mainly to complete the union condition and various pulse output base pin’s choice. The union condition output controls the high repetition frequency using the illumination pulse and repetition frequency signal LPM-COUNTER the function aclr reset signal, with the aim of arriving at the control repetition frequency signal the output. Figure 7 is the union condition simulation profile.
Figure 7 union condition simulation profile
