Contact type image sensor CIS (Contact Image Sensor) is after CCD in the 1990s research and development one kind of new electro-optic coupled apparatus [1]. It electro-optic integrations and so on sensor array, LED light-source array, columnar lens array, shift register and analog switch in a strip square shape box, its principle of work and CCD is more similar, but compares with CCD, CIS has the volume to be small, the price is low, the structure is simple, merits and so on easy installation, at present in domains and so on facsimile machine, scanner and bar code decoder may substitute for the CCD image sensor completely.
This article introduced that one kind (Complex Programmable Logic Device) uses the image gathering system which based on complex programmable logical component CPLD the contact type image sensor realizes.
1 system survey
Image gathering module’s diagram as shown in Figure 1, the CIS image sensor under the CPL control, transmits each picture element’s grey level analogue voltage value’s form through the serial shift way, some picture element electrical signal again after differentiator amplifier electric circuit clear signal recuperation, by a/D switch the analogue voltage transformation digit quantity, will realize double memory block taking turns through main line’s cut to work, then under the CPLD control, after will transform the digital signal interim in memory RAM.
CPLD is system’s core part, mainly completes the control which, the address production the CIS image sensor’s succession actuation, a/D switch’s control, the main line cut, the data memory as well as with DSP processor’s coordinated.
The main line cut is the gathering essential part, realized two which the image data saved to take turns structure [2]. When CPLD writes an image to memory RAM1, DSP reads another image to memory RAM2, when memory RAM1 writes all over, and memory RAM2 reads off time, cuts mutually by the CPLD control read-write main line, continues by CPLD to memory RAM2 to write down an image, DSP reads the preceding image to memory RAM1, uses the design method which this kind of two take turns to cause gathering and processing may also carry on, enhanced the data acquisition and the processing efficiency.
2 hardware constitutions
2.1 CIS contact type image sensor
In this article application, the contact type image sensor’s effective scanning width is 216mm. Its electro-optic detecting element and the columnar lens correspond separately the platoon becomes the array, altogether has 1728 sensing units, to be able take red, green and the infrared three kind of photo sources carries on the scanning to the image, the clock rate as the 4M hertz, the model is C2R2166289.
2.2 A/D switches
TLC5510 is high speed a/d conversion component [3] which American TI Corporation produces, it is one kind uses CMOS the craft manufacture 8 high impedance parallel A/D chip, the biggest sampling may reach 20Msps. Because TLC5510 not only has the high speed A/D transformation function, and has the internal sampling maintains the electric circuit, therefore simplified peripheral circuit’s design greatly, because its interior has the standard voltage-division resistance, thus may obtain the 2V full scale division from the 5V electric power supply the voltage reference.
2.3 CPLD and DSP processors
The CPLD chip selects ALtera Corporation’s MAX7000S series component EPM7128SLC84, this chip may through the JTAG online programming, by 128 logical great units and 2500 available logical gates. In MAX PLUSⅡIn the software, the use high-quality hardware description language programming will design the good hardware logic to download to the chip, causes is similar to hardware’s design the software design same convenience is quick.
The buffer storage by 2 piece of IS61C1024 chip constitution, IS61C1024 is 8 128KB high speed CMOS static RAM, the smallest storage time is 12ns, can satisfy the high speed data read-write the request, simultaneously also suits the large capacity image data the interim.
The DSP chip uses TI Corporation’s TMS320C5402 chip, uses the improvement the Harvard structure, has the low power loss, the high speed real-time signal processing characteristic.
3 CPLD hardware logical function design
CPLD is the image gathering hard core, its positive governing CIS image sensor and a/D switch, complete the digital image data acquisition, the transformation and the memory, as well as with DSP processor’s handshake coordinated.
CPLD module overall function’s principle of design as shown in Figure 2, CPLD produces CIS image sensor’s clock signal CLK (the 4M hertz), the gating signal inputs SI, the red photo source selects LEDr, green photo source gating signal LEDg, the infrared source selects LEDir. When CPLD controls these signals have the corresponding succession, CIS sensor through simulated signal output pin SIG to A/D switch serial shift output correspondence picture element gradation. 
CPLD controls a/D switch’s output to select the OE signal, after causing a/D switch may output transforms the data, simultaneously, CPLD produces data memory address AD [0..16] and writes a letter number WR, A/D switch’s digital image data storage in corresponding memory block.
The main line cut realized two data memory blocks with the double memory block module to take turns the work, its schematic diagram as shown in Figure 3, CPLD realized the double memory block through control memory selection signal E to take turns the work, when on electricity initial, selection signal E was the high level, memory block RAM1 is writes the condition, simultaneously RAM2 the DSP processor’s control, is changed E the condition, realized main line’s cut.
EN, NEXT and READY are between DSP and the CPLD handshake signal, EN are the CPLD work enable the signal, when EN is the low level CPLD only then starts to work. This time, if DSP processor NEXT carries produces a signal impulse, CPLD controls the CIS image sensor to gather a line (1728 picture elements) the image, simultaneously, READY sets 0, expresses is gathering, when a line of image gathering completes, the READY signal restores for the high level, when EN restores for the high level, the CPLD stop work, and selection signal E will take counter-realizes the main line cut, writes the status switching the current memory by CPLD is DSP reads the condition, realizes the double memory block to take turns the work.
4 main lines cut realization
In this article application, the request high speed real-time carries on the image gathering and processing, requests in 40ms to process an image, if gathering and the stored image data has taken the too much time, then the following imagery processing was unable to complete, to reduce the time which as far as possible gathered and save, used two groups of memories in the system to carry on takes turns to save.
In the system, selects the method which the main line cuts to achieve two memory alternately read-write the function, when CPLD outputs a/D switch when the image data reads in RAM1, DSP may read in RAM2 the data and processes the preceding image the data, when CPLD finished an image data, and after DSP completed the preceding image processing, changed CPLD to write the data to RAM2, DSP and CPLD exchanges a secondary storage, so circulated, causes DSP the imagery processing and CIS image gathering may the parallel independent working, has guaranteed the image real-time and with high speed.
In Figure 3, RAM1 and RAM2 are 2 piece of IS61C1024, the constitution dual according to the cushion memory block, M1-M4 respectively are, realizes the address bus hand-off control which constitutes by 74HC16245, N1-N4 is the data bus hand-off control which realizes by 74HC245, C1 and C2 realizes the memory pilot wire (RD to read signal, WR write a letter number and so on) the hand-off control, when choice line E is the high level, M1, M4, N1, N3 and C1 are at the active status, but M2, M3, N2, N4 and C2 are at the high-resistance condition. Therefore the RAM1 data bus, the address bus and the control bus only then the main line and CPLD connect, the RAM2 complete main line and DSP connect. Thus realizes by CPLD writes the data to RAM1, DSP reads the data from RAM2, when choice line E is the low level, then the situation is opposite, DSP reads the data from RAM1, CPLD writes the data to RAM2.
Conclusion
This article depends upon the contact type image sensor, used CPLD and DSP unifies the design to realize has been suitable for the real-time high speed imagery processing image gathering system. In the system, selects the method which two take turns to save, eliminated the DSP standby period, causes the gathering system and the processing system may the parallel independent working, uses the complex programmable logical component, causes the system integration rate to be high, versatile, the connection is simple, and may duplicate programs and the system upgrade, to realize a high speed real-time imagery processing system to provide the foundation.
