Abstract this article narrated to some CCD camera’s image data output interface and the image data pool simulation process. Mainly realizes on the CPLD component, through application based on Channel link technology (LVDS serial/solution string technology) the Camlink standard interface transmission plan, by the LVDS way output signal, may use for finally to examine the image gathering card the active status.
Key words CCD Camlink LVDS CPLD
1 introduction
For many years the CCD component has been small by the volume, the weight is light, the power loss is small, working voltage low and so on anti-overburning characteristics and so on merits as well as in resolution, dynamirange, sensitivity, live transmission, scanning-self, widely applies in photographs the equipment, meteorological, astronautics aviation, the military, the medical service as well as the industry examination and so on numerous domains.
To some multichannel high speed CCD camera outgoing picture signal’s gathering system design process in the middle, we need regarding this systematically before the official use carries on the debugging, whether tests its normal work. This article used CPLD and LVDS has carried on the simulation strictly to the CCD camera’s output interface, and by LVDS way outgoing picture signal.
2 camera system output connection signal and Camera link connection
This CCD camera final output signal conforms to camera the link interface standard, after each channel outputs 3072 elements, then outputs 1024 zero level elements, the data uses the LVDS difference output, each channel’s output signal includes: Control signal: Element clock DCLK, good synchronized signal LVAL and external trigger signal DTRG; Digital image signal (8 bit parallel output) DATA. Various waveform approximately as shown in Figure 1:
Figure 1
· The DCLK element clock rate is 31MHz, has the latter two frequency divisions by the 62MHz crystal oscillator to obtain. By LVDS signal output.
· Good synchronized signal LVAL when outputs 3072 elements and 1024 zero level elements, LVAL is the low level, middle will jump when two effective lines several invalid picture element spots, jump invalid picture element, LVAL will be the high level. A jump picture element number is undecided, supposes initially for the fixed 4 picture elements. By LVDS signal output.
· External trigger signal DTRG is uses for to trigger the gathering card the work, it drops with the LVAL signal along alines, high level width for element clock one cycle width.
As well as will reduce the transmission cost for the enhancement transmission efficiency, the CCD camera above the image signal standards switching low level difference signal (LVDS) will output according to Camera the Link. The system uses National semiconductor which matches with the CCD camera chip set DS90C031W/ML to complete between the TTL level signal and the LDVS signal transformation, transformation connection chip as shown in Figure 2, a connection transformation chip may tally 4 signal conversion 4 pairs TIA/EIA-644 the standard LVDS data stream. In addition has two to enable the end, when work, EN meets the low level, 
meets the high level. This chip’s maximum transmission speed may reach 77.7MHz, the power line voltage is 5V, meets the systematic need. The final output signal receives the image gathering system’s input end. In this article design, only uses the actuation chip, the receive chip to place in the image gathering system circuit.
3 hardware architectures
This design’s hardware circuit is mainly composed of three parts, structure diagram as shown in Figure 3. Including crystal oscillator electric circuit,
CPLD, output interface (9 piece of DS90C031). The entire electric circuit’s hard core is CPLD, uses ALTERA Corporation’s MAX7000S in the series the EPM7128SLC84-15 chip. It besides produces the control signal, but must simulate a gradation image the data pool. the 62MHz crystal oscillator uses for the clock which has the CPLD work to need. DSC90C031 uses for the image signal which and the control signal produces CPLD (the TTL signal) transforms the LVDS signal, and outputs. And every two pieces can produce a channel’s 8 picture output signal, altogether has 4 channels, the 9th piece uses for the switching control signal and outputs.
In circuit design process, to enhance system’s reliability, must pay attention to the following question: 1st, the CPLD component’s each power line voltage base pin wants the external connection 0.1μ electric capacity to carry on the filter. After the CPLD output signal must carry on the filter, receives DSC90C031 again. 2nd, in the out-port, must use the terminal resistance to realize to the difference transmission line biggest match, the resistance number generally in 90–130 ώ, the system also needs this terminal resistance to produce the normal work difference voltage. When necessity may also use 2 resistance numbers respectively for 50Ώ the resistance, and in among through a capacity ground, filters out the syntype noise.
4 CPLD programming
Because considered the design later period must add the monolithic integrated circuit front end CPLD to carry on each kind of control to the image signal change, must therefore use about 50 I/O mouths the operation, therefore has selected ALTERA Corporation’s MAX7000S in the series EPM7128SLC84-15 chip, this chip altogether had 84 pins, the interior integrated 6000, the model available gate was 2500, some 128 logical unit, 60 available I/O mouths, might dispose alone for the input, the output and the bidirectional working, 2 overall situation clocks and an overall situation enabled the end and an overall situation elimination end. It supports the multi-voltage work, its transmission time delay is 7.5ns, the highest operating frequency reaches as high as 125MHz. We use the ALTERA Corporation’s third generation to develop software Max plus II to carry on the simulation, the synthesis and downloading.
The entire procedure is divided three modules: u1, u2, u3, u1 is the frequency division module, (mclk) carries on 2 frequency divisions with 4 output counters to the input 62M master clock, u2 is the image data has the module, has the gradation image data with 8 counters. the u3 module is uses 13 counters to produce the control signal, according to the request succession relations, produces the element clock separately strictly (DCLK), the good synchronized signal (LVAL), the external trigger signal (DTRG). The partial source programs are as follows:
begin
u1:fenpin port map(mclk, clr0, set, clk); // quotation frequency division module
u2:count8 port map(clk, clr1, set, countout8); // quotes 8 counters
u3:count13 port map (clk, clr2, set, countout13); // quotes 13 counters
set<=’1′;
clr1<=’0′;
dclk<=clk;
process(clk)
begin
if (clk’event and clk=’1′)then
if (countout13>=4096 and countout13<=4099) then
lval<=’1′;
data<=countout8;
else
lval<=’0′;
end if;
if(countout13=4099)then
dtrg<=’1′;
clr2<=’1′;
else
dtrg<=’0′;
clr2<=’0′;
end if;
if (countout13>=0 and countout13<=3071) then
data<=countout8; // output effective element
end if;
if (countout13>=3072 and countout13<=4095) then
data<=0; // output zero element
end if;
end if;
end process;
end rtl;
The succession simulation chart following chart shows:
5 summaries
Translation simulation, carries on the synthesis in the top layer with the schematic diagram to realize, however the after-burning enters the chip to carry on the experiment, and according to the actual operational aspect, to designs makes the improvement. If acts according to the actual component’s time delay characteristic, in the design certain place insertion suitable detention unit guaranteed that various latencies are consistent.
Design proposal which introduced according to this article, uses CPLD the technical design the multi-channel CCD image signal simulator structure to be simple, realizes conveniently, easy to revise. In the image gathering card’s test procedure, has played the influential role.
Reference:
[1] Hou Boheng, .VHDL hardware description languages and digital logic circuit design and so on Gu Xin. Xidian University Publishing house, 2004
[2] Yang just, dragon petrel .VHDL and number system design. Electronics industry publishing house, 2004
[3] data sheet of DS90CO31. National Semiconductor .1998
[4] data sheet of MAX7000. ALTERA.2001
