1 introduction
The digital multiple connection is merges the sole closed circuit digital signal two or two above leg digital signal according to the multiple connection way. According to each low order group clock’s situation, the multiple connection has 3 ways: If each input leg digital signal mutual synchronization, and with this aircraft timing signal also synchronization, then the adjustment unit only need adjust the phase, this is the synchronized multiple connection; If input leg digital signal not synchronization, and with this aircraft timing signal also asynchronous, then the adjustment unit must carry on the frequency and the phase adjustment to various legs signal, causes it to become the synchronized signal, this is the asynchronous multiple connection; If the input leg digital signal becomes effective instantaneous is opposite the timing signal which corresponds to this aircraft is by the identical datum speed appears, but speed any change limits in the stipulation tolerance interval, this kind is orbit (PDH) multiple connection [1], this article studies is corresponds two time group multiple connections based on CPLD PDH.
2 two group multiple connection’s basic principle
Two group multiple connections are become 4 2 048 kb/s signal multiple connections 1 8 448 kb/s two group digital signal, its schematic diagram as shown in Figure 1.
The multiple connection by the buffer storage, the inserting control electric circuit, the clock generator, the frequency divider and the multiple connection is composed. The clock producer provides 8 448 kHz clocks; The frequency divider carries on 4 frequency divisions to 8 448 kHz, obtains 2 112 kHz the read-out clocks; The buffer storage and the inserting control electric circuit uses for to make the symbol speed adjustment, same has the tolerance 4 2 048 kb/s legs the datum speed to adjust actually to 2 112 kb/s on, causes their synchronization; The multiple connection was already the synchronized leg signal multiple connection became 4 1 8 448 kb/s two group signal [2].
2.1 digital multiple connection method
The digital multiple connection method has 3 kinds: According to position multiple connection, according to symbol multiple connection, according to frame multiple connection. Because, both need buffer storage’s capacity to be big, at present the application are very few. Therefore this article uses according to the position multiple connection, its schematic drawing as shown in Figure 2.
In the chart, a, b, c, d is 4 leg signals, after e is multiple connection’s two group signal. The multiple connection process is as follows: First takes 4 base groups in turn the 1st position code, afterward takes the 2nd position code in turn again, ex analogia. May see, after the multiple connection, each position code’s width is only the original leg each position code width 1/4, namely the capacity increased 4 times, the base group telephone channel signal capacity is 30 telephone channels, after the multiple connection, is 120 groups. This method is easy and feasible, needs buffer storage’s capacity to be smallest, the existing multiplying equipment selects this method.
2.2 symbol speed adjustment frame structure
By ITU-T suggested that the G.724 recommendation orbit multiple connection two group frame structure like chart 3, shown in Figure 4.
Two group frame sizes are 848 b, divides into 4 groups, each group is 212 b, this 212 b assignment, 4 base groups are similar, take the l base group as the example, frame structure as shown in Figure 3. Divides into 4 groups 212 b, each group of 53 b. ⅠGroup’s 1,2,3 three symbols, for insert the multiple connection frame synchronization code to use, indicated by F; Is 50 b information codes;Ⅱ,Ⅲ,ⅣThe group’s 1st position code serves as the symbol signal, indicated with C; ⅣThe group’s 2nd symbol is the symbol speed adjustment symbol, with V expression, when needs to insert, in this position inserts one not to bring the information pulse, when does not need to insert, this symbol still passed on the information code;Ⅱ,Ⅲ,ⅣGroup’s other positions are the information codes. 4 base group 1~3rd symbol multiple connection in the same place, altogether 12, the first 10 achievement multiple connection’s frame synchronization code, the ll position instructed for the warning, the 12th achievement spare. 4 base group insertion symbol letter number and symbol speed adjustment bit, after the multiple connection, separately links in the same place. Concrete multiple connection frame structure drawing as shown in Figure 4. The multiframe contains bit content following [1]:
(1) locates 10 b, the expression is F11F12~F13F23, the code pattern is 1111010000;
(2) official business 2 b, 1 b (11) use for to send out the warning to the end to instruct; Other 1 b (12) remain makes the domestic use;
(3) leg information 820 b,ⅠThe group is 200 b(13~212),ⅡThe group is 208 b(217~424),ⅢThe group is 208 b(429~636),ⅣThe group is 204 b(645~848);
(4) symbol speed adjusts 4 b, the expression is V1, V2, V3, V4 (641~644), various bases group l b, altogether 4 b;
(5) insertion symbolizes 12 b, indicated by C, filler pulse 4 b. In order to enable the receiving end to know whether to have the insertion and insert in where, while the multiple connection start issues the insertion instruction to need to send out the insertion symbol signal, informs the coupler to have the insertion. Now the commonly used means locate the insertion. Stipulated in here: The 1st base group 1st insertion symbolized that C11 in 213 insertions, the 1st base group 2nd insertion symbolized C12 in 425 insertions, the 1st base group 3rd insertion symbolizes C13 in 637 insertions. Thus it may be known:
C11C21C31C41 (213-216) is the lth insertion symbol;
C12C22C32C42 (425-428) is the 2nd insertion symbol;
Cl3C23C33C43 (637-640) is the 3rd insertion symbol;
The insertion symbolized that the signal is 3, uses 3 position codes to compose the insertion symbol signal, may enhance the symbol signal the reliability. Have the insertion with “111″ the expression, does not have the insertion with “000″ the expression. When C11C12C13 is “111″, expressed that inserts the pulse in 641 time slot’s pulses; When C11C12C13 is “000 “, expressed that in 641 time slot’s pulses is information code [1].
3 VHDL programming and simulation
Introduced based on the above principle that may know the PDH digit multiple connection by the frequency divider, the cushion saves, the inserting control, the mixer and so on several parts to be composed generally, here we use VHDL to carry on the modular programming, entire multiple connection system design 3 parts: The frequency divider, the symbol speed adjustment controller (realizes cushion memory as well as symbol speed phase adjustment insertion), the mixer. Functional block diagram as shown in Figure 5.
3.1 frequency division partial simulation profile
The frequency divider is obtains 8 448 kHz clock 4 frequency divisions 2 112 kHz clocks, provides to the symbol speed adjustment reads out the clock. Its succession simulation profile as shown in Figure 6.
3.2 symbol speed adjustment subprogram design and simulation profile
The symbol speed adjustment is enhanced by multiple connection’s low order group symbol speed, causes its synchronization to some stipulation high symbol speed. Take two group multiple connections as the example, two groups become by a 4 group, a group code rate is 2 048 kb/s, two group’s code rates are 8 448 kb/s, therefore, may act according to the multiple connection frame the request, inserts the person corresponding pulse number, the base group velocity rate adjustment is 2 112 kb/s, then 4 leg merges, may obtain 1 group element speed is 8 448 kb/s two groups. Uses as shown in Figure 7.
The base group input rate is 2 048 kb/s digital signals to a buffer storage, after reading out the clock rate is symbol speed adjustment speed 2 112 kb/s, therefore the memory is at “reads quickly writes slowly” the condition. And Figure 7(b) may see from Figure 7(a), after the first pulse passes through period of time reads out, the second pulse’s read-out passes through the time must be shorter than the former, because the reading speed is quicker than the writing speed, later read-in with read-out time difference, namely phase difference getting smaller, when phase difference slightly to certain extent, (in buffer storage) sends out the insertion by the phase comparator to request, the request insertion pulse control electric circuit issues an insertion instruction, stops a read-out, simultaneously inserts a pulse, like in the chart the dashed line position shows. Inserts the person pulse not to carry the information, should remove in the receiving end him, for this reason, can the transmitting end during insertion pulse’s, which send out a sign signal to inform receiving end inserts the pulse, in order to remove him restores the primary signal.
After the receiving end receives the transmitting end the symbol signal, he passes through a sign signal together with the signal to pick out the electric circuit together to pick out, thus produces one “to disappear inserts the signal”, endures one writing pulse, as shown in Figure 7(c). By now, digital and the original digital order was the same, but the time-gap was non-uniform, must therefore withdraw the clock in the receiving end from chart 7(c), will affect through the phase-locked loop ring circuit will have removed the insertion pulse the number symbol stream uniformization. 4 base group leg’s speed adjusts after 2 112 kb/s, the multiple connection becomes two group [1] again. The symbol speed adjustment production component and succession simulation profile as shown in Figure 8.
3.3 multiple connections (closed circuit) subprogram design and simulation profile
In the chart d1, d2, d3, d4 is in turn the input low order group leg signal, after quik8448 is multiple connection’s two group output signal, reads out clock’s drop in 8 448 kHz along triggering. Reads input signal d1, d2, d3, d4 in 4 clock cycles is in turn “1100 ‘ ‘, next is “1001″, analogizes in turn, the final output is “1100 0110 1001 1111…”.
3.4 comprehensive electric circuits
Synthesizes the above each module, may obtain synthesizes the electric circuit to realize two time group multiple connection function, concrete realizes diagram as shown in Figure 10.
Succession simulation profile as shown in Figure 11. In the chart, IN1, IN2, IN3, IN4 respectively is 4 group 2 048 kb/s leg signals, after 0UT is compound, outputs 8 448 kb/s two group multiple connection signal. In front of the output signal 10 for frame localization bit (1111010000),11, 12 are official business bits, here supposes is “00″, starts from 13 for the information bit, reads the person input signal in turn according to 2 048 kHz clocks, according to reads out clock 8 448 kHz to read out the compound latter two group signal is “1010 1110 1110 1111…”. May see system’s design and the simulation and the theory forecast match case by the simulation result.
4 conclusions
The digital multiple connection technology is not only and the source encoding, the digital transmission, a digital switching abreast row skill, moreover in net synchronization frame adjustment, in line concentrator’s line in multiplying as well as digital switching technical and so on connection foundations, therefore, the digital multiplying technology is in digital communication foundation technology [3].
In former PDH multiple circuit, what system’s many parts use is the analogous circuit, therefore has the very big limitation. But this article realized multiple connection has broken these limitations based on CPLD the technical PDH, had the design cycle to be short, the revision convenient, does not have the special-purpose chip function limit, the reliability and the integration rate higher merit, was the present system designers’ priority selection. Enhances unceasingly along with the programmable logical component performance, the development system consummates unceasingly, the programmable logical component in the electricity gives in the engineering design the application to be surely getting more and more widespread.
