Abstract: This article introduced one kind based on FPGA the technical IDE hard disk connection design. This card provides two to conform to the ATA-6 standard connection, used FPGA to realize two set of IDE interface function, the design has supported PIO and Ultra the DMA mode of transmission, the article stresses in the introduction realizes the IDE connection agreement concrete method with FPGA.
Key word: FPGA; Hard disk; IDE connection

Introduction

    This article used FPGA to realize the IDE hard disk connection agreement. The system provides two sets to conform to ATA-6 the standard IDE connection, with the ordinary IDE hard disk connection, another is connected with the computer motherboard’s on IDE connection. The system uses FPGA to realize the connection agreement, completes the interface data the interception, processing (is mainly in this paper data encryption) and the repeater, supports PIO and Ultra the DMA two kind of data transmission pattern. Below introduced with emphasis realizes the connection agreement method with FPGA.

1 IDE connection agreement synopsis

1.1 IDE connection pin definition

    IDE (Integrated Drive Electronics) namely “electronic integration driver”, is also called the ATA connection. Table 1 has listed in the ATA standard on the IDE connection signal. And, belt “-” the signal (for example RESET-) expressed that the low level is effective. “the direction” is opposite in the hard disk says, I expression enters the hard disk, O expressed that comes out from the hard disk, I/O expresses bidirectional.

Table 1:IDE connection pin definition

1.2 IDE controller’s register group

    The main engine is realizes to the IDE hard disk’s control through hard disk controller’s on two groups of registers. A group to order the register group; Another group/diagnoses the register for the control, as shown in Table 2.

    In the characteristic register’s content takes the order a parameter, its function changes along with the order. The sector number register instructed that this order must transmit the data sector number. Sector number register, cylinder number register (low, high), driver/magnetic head register three hecheng for medium address register, instructed that this order must transmit the data first sector address, the addressing system may use “the cylinder/magnetic head/sector (CHS)” or “the logical block address (LBA)” the way, assigns in the driver/magnetic head register.

    Orders the register to save the execution the order code. When to orders the register reads in the order, the related parameter must first read. After the order reads, the hard disk starts the execution which immediately orders. After condition register preservation hard disk executive command result, for main engine read. Its main position includes: The BSY- driver is busy, the DRDY- driver prepares, the DF- driver breakdown, the DRQ- data request, the ERR- order execution makes a mistake. The auxiliary condition register and the condition register’s content is completely same, but reads time this register does not eliminate the interrupt request. The wrong register has contained the order execution makes a mistake when hard disk’s diagnostic message.

    The data register is under the PIO mode of transmission, the main engine and between hard disk controller’s buffer carries on the data exchange the register. The data port is under the DMA mode of transmission the special-purpose data-transmission channel.

1.3 IDE data transmission way

    IDE connection data transmission including PIO and DMA two ways. The PIO pattern is the hard disk data transmission basic mode. Under the PIO way, the data transmission take the block data (1 or many sectors) as a unit, transmits a block data after every time, the hard disk can have an interrupt request, and to the main engine reported that the order carries out the result.

    Under the DMA way, between the main engine and the hard disk needs to establish a DMA channel through a series of handshake signal, the data by the data stream form transmission. When transmits an order all data, the hard disk has an interrupt request, and to the main engine reported that the order carries out the result. The DMA way divides into Ultra DMA and Multiword the DMA two kinds. Ultra the DMA way along along locks the data in gating signal’s rise with the drop, raised the data transmission speed, and in data transmission conclusion time must carry on the CRC verification.

2 FPGA interior diagram

    This design uses Actel Corporation’s ProASIC PLUS the series FPGA chip, its internal diagram as shown in Figure 1.

    A register group preservation the order which and the command parameter reads from the main engine, retransmits under control module’s function gives the hard disk. The register group two preservation carry out the result from the hard disk read-out’s order, for main engine read. The control module is responsible to produce to the main engine and to hard disk’s each kind of IDE agreement control signal, and is coordinated between various modules the work. The control module uses state machine’s design method, its software design flow in next detailed introduction. The data processing unit carries on to the data adds/the decipher operation. Buffer one, two piece of achievement data processing unit input/output buffer. Under the PIO way, data processing take the block data as the unit, the buffer acts as RAM the function; In Ultra under the DMA way, the data by the data stream formal treatment, the buffer acts as FIFO the function.

3 system software flows

    When starting, FPGA examines the reset signal, the initialization internal register group, and carries on the replacement operation to the hard disk, after the hard disk repositions finished, FPGA to enter the idling condition. FPGA when idling condition will examine the main engine whether to have writes the command operation (usual order read-, must write characteristic register, sector number register, sector number register, cylinder number low position register, cylinder number top digit register, driver/magnetic head register 6 command parameter register first, finally will order to read in orders register). As soon as when after the main engine finished in turn the register group, FPGA sets at the BSY position to the main engine, and will order the repeater to give the hard disk, simultaneously judges the order type, according to the different order, enters the corresponding demand processing flow.

    If is the non-data command, FPGA waited for the hard disk order the execution, after the order execution finished, the hard disk had an interrupt request, this time FPGA will carry out the result read-in register group in two, and had the interrupt request to the main engine. If has the data command, according to data transmission’s pattern, separately enters to the following PIO demand processing flow and Ultra the DMA demand processing flow.

3.1 PIO demand processing flow

    Has Write Sectors, Write Multiple, Read Sectors and Read Multiple by the PIO pattern transmission data’s order. When FPGA judges is the PIO pattern data transmission order, changes the PIO demand processing flow. Below we write the operation take PIO as the example introduction.

    FPGA first inquires hard disk’s BSY position. If BSY is 0 pieces hard disk’s condition register read-in register group two, and inquires the DRQ position. If DRQ is 1 piece indicated that the hard disk has prepared to receive the data. This time as soon as the main engine may read in the block data to the buffer (in this design, we establish block data size are 1 sector altogether 512 bytes). After the main engine finished a block data, FPGA set at the BSY position to the main engine, the data processing unit starts to carry on the encryption operation, after and will encrypt the data to read in the buffer two. After the encryption operation completes, FPGA reads in the buffer two data the hard disk data buffer area, and enters the waiting status. After hard disk reads in the data the physical medium (diskette), will produce an interrupt request, reported already completes this block data to write the operation. FPGA will carry out the result read-in register group in two, has the interrupt request to the main engine, and inquires the DRQ position once more, if DRQ is 1 piece enters the next PIO block data the transmission process, if DRQ is 0 pieces expressed that this order all data all pass on, FPGA enters the idling condition.

    In addition, Identify the Device order is the main engine reads out 512 bytes attribute information by the PIO way from the hard disk (including hard disk’s model, capacity and so on). This time, the data processing unit does not deal with this order the data to carry on adds/the decipher operation.

3.2 Ultra DMA demand processing flow

    Pattern transmission data’s order has Write DMA and Read DMA by Ultra the DMA. Below we write the operation take Ultra DMA to introduce Ultra as the example the DMA demand processing flow.

    The DMA transmission path’s establishment is requests by the hard disk through DMARQ. After FPGA receives hard disk’s DMA request, the first initialization main engine to the FPGA DMA channel, is following closely initialization FPGA to hard disk’s DMA channel. This time the main engine namely has established after FPGA to hard disk’s DMA channel, the main engine to a buffer write data, simultaneously the data processing unit carries on the encryption operation to the data, after and will encrypt the data to read in the buffer two, FPGA reads in the buffer two data the hard disk. In transmission process, if the hard disk request suspends or the buffer two spatial, then FPGA suspends to the hard disk transmission data; If buffer one full, then FPGA requests the main engine to suspend the transmission data.

    The main engine and the hard disk may momentarily stop the current DMA transmission, has not passed on the data will wait for when hard disk next time DMA request carries on the transmission again. If the hard disk proposes stops transmitting, FPGA will remove FPGA to hard disk’s DMA channel, simultaneously proposes to the main engine stops transmitting, removes the main engine to the FPGA DMA channel, and calculates this time to pass on the data the CRC verification. Then FPGA enters the waiting status, waits for the hard disk next time DMA request.

    If the main engine proposes stops transmitting, FPGA will remove the main engine to the FPGA DMA channel, simultaneously continues to the hard disk transmission data, until will receive main engine’s data end of transmission, after namely buffer two spatial, proposes to the hard disk stops transmitting, removes FPGA to hard disk’s DMA channel, and calculates the CRC verification. Then FPGA enters the waiting status, waits for the hard disk next time DMA request.

    Under waiting status, if FPGA receives hard disk’s interrupt request, then explained that this order all data already passed on, the order ended. FPGA will order to carry out the result read-in register group two, has the interrupt request to the main engine, enters the idling condition. If receives hard disk’s DMA to request, then explained that the hard disk has not received this order all data, this time needs to judge the main engine whether to have possessed the data to transmit. If the main engine will not have possessed the data to transmit, then establishes FPGA once more both sides the DMA channel, starts the new round DMA transmission; If the main engine will have possessed the data to transmit, then establishes FPGA to hard disk’s DMA channel, until transmits the buffer two data, and calculates the CRC verification.

4 concluding remark

    This article used FPGA to realize two sets to conform to ATA-6 the standard IDE connection, completed between the main engine and the hard disk the data interception, processing and the repeater. After the test, the system in DOS, Windows 98, Windows 2000, Windows XP and Red Hat under the Linux 9.0 operating system environment, the use hopes Czechoslovakia, to step develops, Tristar, west company’s and so on number many kinds of model hard disks to work normally, supports PIO and Ultra the DMA two kind of data transmission pattern. Because realizes a complete IDE connection through FPGA, if modifies slightly to the system, like joins the corresponding filing system in the data processing unit, then realizes the off-line read-write IDE hard disk, uses in the data acquisition the mass memory and so on many kinds of situations, enables the system to have the good versatility.

    This article author innovates the spot: The author easy to divulge a secret and in view of the hard disk data questions and so on high speed large capacity data acquisition difficulty, proposed that uses the FPGA chip between the main engine and the hard disk to construct a bidirectional IDE hard disk channel, realizes two sets to conform to ATA-6 the standard IDE connection, FPGA carries on processing and the repeater data stream to between the main engine and hard disk’s, realizes hard disk operations and so on data encryption, data high speed gathering memory and off-line control hard disk. The system supports PIO and Ultra the DMA two kind of data transmission pattern, is transparent to the operating system, the common unidirectional IDE channel, this system versatile, have the good promoted value. This article stresses in using FPGA to realize the IDE connection agreement, to realized the process and the method has made the detailed description, had the high reference use value to the reader.

Reference:

1 T13 Technical Committee.  Information Technology-AT Attachment with Packed Interface-6 (ATA/ATAPI-6). [S] Revision 1e.  2001
2 Friedhelm Schmidt, the outstanding person science and technology translates, SCSI main line and IDE connection: Agreement, application and programming (the second edition), [M] China Electric power Publishing house, 2001.3
3 Actel Corporation.  Libero User’s Guide.  2004
4         Actel Corporation, Pro ASIC PLUS Data sheet, Version v3.5,2004.4
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