Abstract: This article has summarized the decision feedback equalizer basic principle and realizes the way, to realize the balancer to be possible satisfiedly to dispose the need, aims at the decision feedback equalizer specially the multiple structure, proposed that one kind uses the modulation design method from bottom to top, has carried on the exhaustive analysis to system’s each module design, and discussed the main point which needs to pay attention.
Key word: Decision feedback equalizer, DFE, FPGA, design method
1. Introduction
When the mobile communication and the high speed wireless data communication, the multi-diameter effect and channel bandwidth’s finiteness as well as the channel characteristic imperfect cause the data transmission the inevitable production intersymbol interference, becomes the influence correspondence quality the primary factor, but channel’s balanced technology may eliminate the intersymbol interference and the noise, and reduces the error rate. And the decision feedback equalizer (DFE) is one kind very effective and applies is widespread copes with the multi-diameter disturbance to result in the measure. At present DFE has following several kinds to realize the method approximately: 1) selects many piece of general digital filter integrated circuit cascade method, but simultaneously by brings with many pieces the volume and power loss increase, the utilization are not in reality many. 2) uses DSP to realize, if Motorola SC140 is the monolithic programmable balancer, uses the software to realize the algorithm, but as a result of the component function limit, is received in the timely request extremely high situation the limit. 3) uses the programmable logical component to realize, along with the programmable logical component logical gate quantity and speed unceasing increase, realized the system integration on monolithic already to become possibly, moreover the FPGA especially qualify realized the decision feedback equalizer which might dispose.
2. decision feedback equalizer basic principle
The decision feedback equalizer (DFE) is one kind of misalignment balancer. As shown in Figure 1, (is composed and the feedback part of the forward feed part by the FIR filter) (is composed of the IIR filter) composes, the forward feed part may counter-balance in the time the intersymbol interference and in the time in advance is the lag intersymbol interference (by center tap’s position decision), the feedback part may counter-balance the intersymbol interference which lags in the time.
The balancer output is: 
In the formula M, N respectively be forward feed filter and feedback filter’s length. The tap coefficient renewal uses DD_LMS (direct decision least mean square) and CMA (constant modulus algorithm) the algorithm, CMA is one blind auto-adapted algorithm, namely does not need the training sequence, may let the balancer restrain to the low MSE level, but because the CMA extent of the error is big, thus the length of stride is small, the CMA track capacity is limited, thus, in the DFE design, CMA frequently as the balancer initialization algorithm, namely carries on the rough estimate to the multi-diameter signal’s latency and the scope. But the DD_LMS algorithm is opposite in CMA has the lower MSE level, and DD_LMS has the low extent of the error, thus the length of stride is bigger, track capacity, thus, in the DFE design, DD_LMS frequently after balancer stable auto-adapted algorithm.
3. design concept
Because we design DFE is a quite complex system, we carry on administrative levels from bottom to top in the design according to the function block, like this may save the design time, reduces the design input the mistake, eliminates the redundant circuit element, and can simplify the verification to make the revision, in the actual design, divides into three parts according to the module size and the function: As shown in Figure two, PART I includes the connection and the DFE balancer, PART II includes the decision and the error control function operation module, PART III for the tap coefficient adjustment part.
Stemming from the flexible consideration, the system uses is similar to the collection and distribution control, but non-common control plan, is also a system not central control unit, like this may maintain three partial relative independences, if the change design, for instance the change algorithm, only needs to change the error control function operation module then. The various modules’ appropriate division increased system’s flexibility greatly.
4. various modules’ FPGA realizes
4.1 interface modules
This system has not involved the concrete A/D component, only acts according to the commonly used A/D component’s work signal design system interface module.
After the transformation completes, generally a/D component outputs a low level signal to take A/D the permission signal. This signal in the system for input signal ad_end, the interface module system clock monitors ad_end throughout the level fluctuation, when examines ad_end the low level, the interface module produces one “the start” the pulse to take the permission signal, permits DFE the detention link receive data-, and starts to shift. It realizes as shown in Figure three.
4.2 DFE modules
The balancer divides into FFE (Feedforward Equalizer) and FBE (FeedBackward Equalizer) two parts, the structure is similar, the forward feed filter are 32 step FIR filter, the feedback filter are 64 step IIR filter, the filter coefficient width are 16, the precision are 15, the data-in width are 12, the precision are 10, the decision output data are 2, the precision are 0, this module is mainly composed of the input shift register and the convolution module.
(1) inputs the shift register
Regarding forward feed filter, because altogether has 32 steps, therefore input register’s length is 32. Defines 32×12 two-dimension array FFF[32][12], when the reset signal is effective, FFF resets. The reset signal is invalid, when inputs enables the signal is effective, every time comes a clock to rise along, enters a data from the input end, on one time’s data moves ahead one separately, the forefront data by the second data cover.
Regarding feedback filter, because has 64 steps, therefore input register’s length is 64, defines 64×12 two-dimension array FFF[64][12], the data entry mode and the forward feed filter is the same.
(2) convolution part realization
Regarding the forward feed filter, the data-in width is 12, the precision is 10, the filter coefficient width is 16, the precision is 15, the data-in is the belt sign digit, the data top digit is a sign bit, to realize the multiplication operation, the design 12×16 position’s multiplier, separately takes out the data and the coefficient take 12×16 the input from the forward feed input shift register and in the forward feed coefficient shift register, such 32 multipliers respectively obtain 32 products, the product width are 11 15, after the precision is 10 and 15 data multiplications, obtains the data precision is 25, therefore result decimal point between 25th and 26. For the reduced system’s hardware expenses, carry on multiplier’s output result the reasonable interception, takes the precision is 15, low 10 discarding, such multiplier’s output becomes from 11th to the 27th data, the width is 17, the precision is 15. The feedback filter realizes with it is similar.
4.3 error control function operation module
The error control function operation module mainly completes the decision output as well as the error control function operation. The different tap renews the algorithm to lie in the error control function the difference. The decision function is carries on the error to decide, the decision decision part is quite simple, because the binary number uses the complement representation, the decision and error’s computation may use the combination circuit to realize.
4.4 tap coefficient adjustment module
This module completes the tap coefficient the auto-adapted adjustment, the module is mainly composed of the coefficient shift register and the coefficient adjustment operation module.
(1) coefficient shift register
Regarding the forward feed register, the corresponding input shift register has 32, then the coefficient shift register also has 32. Establishes an initial coefficient to load the out-port, when 32 coefficient input ends, 32 coefficient out-ports, the reset signal is effective, all register reset, the initial coefficient serial loads, loads 7 initial coefficients to need 7 clock cycles, when loads enables to be effective, every time comes a clock to rise along, loads a coefficient, loads the first coefficient moves a register right, if the coefficient adjustment enables effectively, then comes a clock to rise every time after comes from the coefficient adjustment operation module adjustment the coefficient parallel loads to the coefficient shift register.
Regarding the feedback factor, the shift register has 64, the shifting principle same forward feed filter.
(2) coefficient operation adjustment
The tap coefficient’s adjustment may calculate according to above equation, 
time ago tap coefficient vector, 
for time feedback tap coefficient vector, 
for data-in vector, 
for decision output vector, 
for error control functional calculus module output.
Regarding the forward feed tap coefficient, the input preceding time’s coefficient the coefficient which outputs from the forward feed coefficient shift register, comes a clock, the coefficient to adjust one time every time.
For width 12, the precision is 10 data, 
for the width is nine, the precision is 0 data, both input after a 12×9 multiplier multiplication, obtains the width is the 11 8 1=20 position, the precision is 10 data. Because calculates in the error control module 
time, has only taken low 9, decimal point right lateral 15, now shifts to the left the decimal point 15 to obtain the width is 26, the precision is 25 data. Intercepts high 16, obtains the width is 16, precisions is 15 coefficient adjustment quantity. The preceding time’s coefficient and this adjustment quantity input to 16 single-order subtractors, here coefficient is minimum, therefore does not need to consider carrying, obtains a width is 16, the precision is 15 difference, after namely the adjustment coefficient, outputs the forward feed coefficient shift register.
Regarding the feedback tap coefficient, the input preceding time’s coefficient the coefficient which outputs from the feedback factor shift register. Comes a clock, the coefficient to adjust one time every time.
For the width is 2, precisions is 0 data, for width 9, the precision 0 data, both input after a 2×9 multiplier multiplication, obtains the width is the 1 8 1=10 position, the precision is 0 products. Similarly shifts to the left the decimal point 15, obtains the coefficient adjustment quantity. The preceding time’s coefficient and this adjustment quantity input to 16 single-order subtractors, after obtaining an adjustment coefficient, width 16, precision 15.
4.5 FPGA realizes
Entire designs uses verilog the HDL language to realize completely, the FPGA chip uses XC2VP70, uses Synplify Pro 7.7 to carry on the synthesis, ncverilog 5.0 carries on the function simulation, the ISE6.3 production wiring document. To designed according to the synthesis result has carried on the optimization, finally the system demonstrated that the upper frequency might arrive at 80M, boarded up the test function to be normal, the system delayed control in the 35us scope, might satisfy the overwhelming majority high speed wireless data communication system to the balancer request.
5 summaries
This article author innovates the spot: In view of the high speed wireless data communication’s timely request, proposed that uses FPGA to realize may dispose the balancer the design, uses in the design process from goes against, but under divides the design way, namely has facilitated the design need, simultaneously has satisfied the performance request, receives the very good effect in the actual project.
Reference:
[1] Zhao Wenbing, “FIR Filter’s Realization And Simulation Research”, micro computer information, in 2005 the seventh issue, P108-109
[2] Zhang Yuliang, “Improvement Decision Feedback equalizer Performance One New Method”, Radio Communications Technology, in 2003 the fifth issue, P22-24
[3] the Zhao esthetic pleasure, “One Kind Is suitable Blind Balanced Algorithm which Realizes in FPGA”, Journal of China Institute of Communications, in 2001 the eighth issue, P108-112
