Abstract: The programmable logical component CPLD volume small function is formidable, Verilog the HDL language is succinct, the design concept, the circuit structure and the logical relation are clear, this article introduced emphatically uses Verilog to design CPLD to realize the duplex diode demonstration liquid crystal controller’s function.
Key word: Verilog CPLD liquid crystal controller
1. introduction
Along with the integrated circuit technology’s development, in the modern electron design, the programmable logical component’s utilization are getting more and more, the reason lies in its scale to be big, the volume is small, function, the price is cheap. CPLD may scratch writes over ten thousand times, causes the hardware design software design equally to be likely nimble conveniently. Verilog the HDL language has its unique superiority as the hardware description language: In the gate level description’s first floor, the description design concept, the circuit structure and the logical relation clear perspicuity, the design language succinct, easy to study easily to use, modulation stratification structure when large-scale design has the superiority. If uses Verilog the control function integration in a piece of CPLD chip, the entire electric circuit will become more succinct, practical.
2. liquid crystal controller principle
The liquid crystal controller uses in the monolithic integrated circuit and the liquid crystal box connection, on the one hand obviously saves unceasingly data refurbishing to liquid crystal box, on the other hand controls the monolithic integrated circuit to obviously to save the data the renewal.
The duplex diode structure liquid crystal controller interior main counter, respectively is the 4bit clock synchronized character counter, the good counter and the frame counter, they under system clock FCLK control coincidence circuit, is mainly uses for to produce good synchronized signal LP and frame synchronizing signal FP, uses for to control the liquid crystal box separately to line feed with the form feed. In the liquid crystal box is obviously saves repeatedly under these three signal control data refurbishing to the screen on.
This design uses the EPM7128SCPLD chip which Altera Corporation produces to realize the LCD controller as well as its periphery logic succession complete function, the use liquid crystal box for 640×480 the duplex diode demonstration structure, namely the first half screen and the second half screen also demonstrated that RAM is one piece SRM20512LLTM78(62512).
The liquid crystal box refurbishing speed’s formula is FFRP = FCLK/(Hn×Nx).
And, FFRP is the liquid crystal box demonstration vertical sweep frequency, generally must be bigger than 70 Hz, Hn is a line of demonstration 4bit synchronized character counts 640/4=160, Nx is screen frame scanner number of lines 480/2=240, FCLK is system’s work clock rate, uses the crystal oscillator to provide frequency 11.05926MHz, obtains 2.764815MHz its four frequency divisions then to take system clock FCLK.
The system constitution following chart shows:
3. realizes the process
1) liquid crystal refurbishing succession production
This part mainly has the good synchronization and the frame synchronizing signal, forms a line with the frame synchronization.
Because the duplex diode structure liquid crystal box as the unit also demonstrated up and down take 4bit, may define two registers in CPLD, the line including 4bit character register scp_reg, the value is 640/4=160, the frame contains good register lp_reg, the value is 480/2=240. Character clock synchronous counter scp_count is the 4bit character counter, counts under the system clock scp_clk function adds one, compares with the line including the character register content, if and so on, expressed that line of conclusions, started the next line, the scp_count reset, good counter lp_count added one, lp_flag set one, produced good synchronized signal LP. Good counter lp_count and the frame compare including the good register content, if and so on, expressed that a conclusion, started next, scp_count, the lp_count reset, fp_flag sets one, produced frame synchronizing signal FP. Realizes the procedure is as follows:
always@ (posedge scp_clk)
begin
scp_count=scp_count 1;
if(scp_count==scp_reg)
begin
lp_count=lp_count 1;
lp_flag=1;
scp_count=0;
if(lp_count==lp_reg)
begin
fp_flag=1;
lp_count=0;
scp_count=0;
end
else fp_flag=0;
end
else lp_flag=0;
end
When operates lcd, scp_reg=160, lp_reg=240. When simulation takes scp_reg=3, lp_reg=4, as follows:
2) the monolithic integrated circuit writes the data to RAM
This part renews the RAM data for the monolithic integrated circuit through CPLD.
The monolithic integrated circuit writes a letter number WR to be effective, in CPLD judgment data line content for instruction or data, if is the instruction, stores the DB content instruction register CMDREG, if is the data, the judgment instruction register CMDREG content instructs the condition. If CMDREG is 8 ‘ h00 or 8 ‘ h02, indicated that DB is low or the high eight bit address, stores low high eight bit address register addl and addh separately, if is 8 ‘ h04, indicated that DB is must read in RAM the data, log data register ioreg.
|
CMDREG |
DB content |
|
8 ‘ h00 |
Low eight bit address |
|
8 ‘ h02 |
High eight bit address |
|
8 ‘ h04 |
Data |
if(a0==1) cmdreg=db;
else begin
if (cmdreg==8′h00) addl=db;
else if (cmdreg==8′h02)
begin
addh=db;
p={addh, addl};
end
else if (cmdreg==8′h04) ioreg=db;
end
3) obviously saves data refurbishing liquid crystal box
This part completes the RAM data to the LCD correct mapping.
The RAM memory and the LCD corresponding relationships following chart shows:
Correct sends in the RAM in data LCD, causes in the liquid crystal box the second half screen also to demonstrate along with the clock, must clear off the RAM memory and the LCD demonstration address relations. LCD is 640×480, therefore the second half screen start address correspondence’s content should for 640×240/8=19200, namely in the RAM0×4b00 content.
Because 4bit character timing clock scp_clk contains four cyclical computerclk, may in the computerclk 23 cycles, separately and 0×4b00 content EF passes on RAM address 0×0000 content AB to eight register reg1 and reg2, in addition the fourth week time, will be A and E passes on reg1 and reg2 high four supreme second half screen data register ud_reg and ld_reg, lcd will demonstrate simultaneously first half screen A second half screen E. When next scp_clk, only need be B and F passes on reg1 and reg2 low four to ud_reg and ld_reg, then lcd will demonstrate simultaneously first half screen B second half screen F. Later every two scp_clk, RAM address will add one, the similar way will take data refurbishing lcd.
After the simulation chart the blue line instruction is the RAM address adds, an above circulation the start.
4) data selector
The monolithic integrated circuit to the RAM data’s renewal, CPLD refurbishing LCD to the RAM read, may two choose a data selector through one to complete.
When the monolithic integrated circuit writes, sets at selection signal sel is 1, deposits MCU the operation address register addl, addh and data register ioreg and the RAM address data bus connection, completes MCU to the RAM data renewal; When sel is 0, refurbishing liquid crystal box address register q and data register ud_reg, ld_reg and RAM address data bus connection, refurbishing LCD.
4. concluding remark
The above mainly introduced Verilog HDL designs CPLD to take liquid crystal controller’s several major components, undergoes the confirmation, designs the controller to complete the liquid crystal correctly under the monolithic integrated circuit function the demonstration. This design innovation spot lies in controller design use hardware description language Verilog, but the alternative design method design, easy to understand, easy to maintain, debugs the electric circuit speed to be quick, many easy to grasp simulation synthesis layout wiring tool. If uses other liquid crystal boxes, only need in the updated program to be related the parameter, multi-purpose expansions, also only need increase in CPLD the module then to realize.
Reference
1. Xia Yuwen. Verilog number system design course [M]. Beijing: Beijing Astronautics Aviation University Publishing house, 2003.
2. Li Preservation. Liquid crystal display applied technology [M]. Beijing: Electronics industry publishing house, 2001.300-350.
3. the week renders meritorious service, Xia Yuwen. Monolithic integrated circuit and CPLD synthesis applied technology [M]. Beijing: Beijing Astronautics Aviation University Publishing house .2003.
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