1 introduction
The change of demand repetition interval and the output pulse integer’s pulse output electric circuit module has the utilization in many industrial fields. Uses the pulse which the digital component design cycle and the output integer may adjust to have the module is the convenience is feasible. In order to enable it to have, the nimble merit high speed, this article used Atelra Corporation’s programmable chip FPGA to design one section of cycle and the output integer invariable pulse generator. Obtains the good movement effect after the board level debugging.
2 system design mentality
The pulse cycle constitutes together by the high level duration and the low level duration, to change the cycle, uses two counters to control the high level duration and the low level duration separately. The counter uses may the parallel load starting value N subtraction counter. Hypothesis: When requests the high level time loads by the starting value after the first subtracter, the subtracter starts to reduce the counting, counts to the zero hour automatic stopping, simultaneously starts the second record low level duration the counter time. When the second subtraction counter also reduces counts the zero hour, counter automatic stopping. This completes a pulse the output, but this pulse’s periodic control definitely may carry on the effective hypothesis in the counter starting value. Serves the repetition interval adjustable purpose. For the steering impulse integer’s output, designs a quantity control counter on the pulse output channel, carries on the counting to the pulse integer, when counts to the request output integer. Completes outputs and gives a done signal to take this module completion of work the symbol signal. Seals good pulse generator design diagram like chart l to show.
The pin signal explained:
start signal: Start signal.
reset, signal: System reset signal.
clock signal: System clock signal.
high signal: High level duration starting value.
low signal: Low level duration starting value.
num signal: Integer control register starting value.
output signal: Pulse output signal. When initialization for low.
done signal: Pulse output symbol signal.
3 height level timer design
3.1 design methods
In order to produce requires the time the high level, may use one to be possible to initialize the number the subtraction counter to serve the purpose, the counter design divides into two parts, a part is may initialize the number from the control subtraction counter: After another part is the subtraction counter completion of work examination system, after examining counter completion of work, outputs a clock cycle wide pulse to take this counter completion of work signal, and may take the next counter work the start signal. Functional block diagram as shown in Figure 2.
3.2 principles of work
First. Exterior reset signal reset gives a clock cycle wide pulse, replacement interior each signal and the trigger.
Then, in the next effective clock time, the exterior start signal gives a clock cycle width the pulse, uses for to start the counter the work. In design, when the start signal is effective (design for high effective), exterior data high loads Q, when Q is not a zero hour, output signal pulse the jump will be the high level, when Q reduces to zero time, the pulse signal jumps again the low level. This signal impulse’s back edge following the detecting element capture which will constitute by two D triggers, and in pulse signal drop after will produce a clock cycle wide pulse, the definition is the done signal, indicated that this signal will complete the output.
The low level timer’s design and the high level timer are completely same. 3.3 succession simulations
In QuartusⅡ4.1 develop in the platform to simulate this module two output signals, the succession imitates eternal truth shown in Figure 3.
May see from the chart, the done signal after the pulse signal output completes outputs a clock cycle width. Completes signal done under this to add to the first-level similar subtraction counter start signal. Under the start the first-level counter work. If under first-level will complete the signal done load to give this level start signal. Will restart a pulse the production. So the autocycle will achieve the uninterrupted output certain recurrent pulse the goal.
4 quantity control counter design
4.1 design methods
The quantity control counter design and the height level counter is similar. The difference lies, subtraction counter clock input termination pulse output signal, when the request output pulse’s integer arrives, outputs gating signal door, the following two D trigger still used for to catch the gating signal door back edge. Once the output integer arrives, the done signal outputs a clock cycle width the pulse to take the symbol immediately. Concrete design diagram as shown in Figure 4.
4.2 succession simulations
In QuartusⅡ4.1 develop in the platform the soft simulation, produces each pulse start signal the pulse generator to take quantity controller’s input signal, simulation result as shown in Figure 5.
After each time output end of mission. Output a OV marker this raid of duty by the overall module to finish. The OV signal may load once more to the total reset signal on, namely this raid of output completes may reposition enters the next raid of duty the output. Figure 5 the door signal presented the very narrow burr, this is because the internal counter’s turn over synchronization does not create. Adds the synchronizing circuit to be possible to eliminate, but will affect electric circuit’s operating frequency. Because the burr is very narrow, does not have any influence to the entire electric circuit work. Therefore, in this module design has not processed.
5 internal signal connections and working
According to each module’s function and the logical relation, by the high level timer, the low level timer and the quantity control counter may build the entire recurrent pulse generator. Its internal circuit according to Figure 6 way connection.
First, along gives a clock cycle width in the clock signal rise the reset signal to reposition the entire electric circuit’s trigger and each output signal. When start signal start along is examined in clock’s rise at the appointed time, the high level starts to time, the time length is equal to the high value and the clock cycle product. When times arrives, the high level timer stops the work, the high level timer outputs one to complete the signal, this signal meets on the low level timer’s start signal foot, starts the low level timer, when the low level timer time completes, the low level timer stops the work, and outputs one to complete the signal, this signal meets through the or gate in the high level timer’s start signal foot, starts the high level timer once more, starts the second pulse high level output. Because the low level timer completes the signal also to connect on the quantity control counter start pin. Therefore, at the same time, the quantity control counter starts to its input pulse s_input to carry on quantity monitor. When pulse output quantity has not achieved the predetermined integer (in quantity control counter starting value), gating signal door has output ” high “, allows the pulse to pass. Once pulse output’s quantity achieves time the predetermined integer, the gating signal door output becomes ” lowly “, the shutting down output channel, and outputs an end of mission symbol signal done. done through or gate connection on overall situation reset signal reset, therefore, after the system completes, then repositions to the original condition waiting next start signal approaches.
The recurrent pulse generator module overall succession imitates eternal truth shown in Figure 7.
Figure 7 has simulated two group pulse outputs, the first group outputs two pulses, the second group outputs a pulse, when two groups pulses both output completes, system recovery to original state. After but when the start signal gives a tripping pulse once more, will again carry out a task.
6 concluding remark
Sees from the analogue result, this article gives the design definitely may achieve the design requirements. Because the FPGA running rate is highest may achieve 100 MHz magnitudes, the output pulse adjustment length of stride and the minimum width may arrive at the ns magnitude. Based on this, the author has designed a multi-channel adjustable repetition interval sequence circuit, and using in group bunch of granule nuclear physics experiment. Receives the satisfactory effect.
