Abstract: Based on FPGA and the electronic design automation technology, uses the modular design the method and the VHDL language, designs one based on the FPGA RISC microprocessor. This microprocessor mainly by the controller, the logic unit and the register is composed, has the command control, the work management, the timing control and the data smoothing and so on basic function, its command length is 16 fixed-length, uses immediately the addressing and the direct addressing two ways. The simulation result indicated that based on the FPGA RISC microprocessor’s clock rate is 23.02MHz, and the function achieves the design requirements completely.
Key word: RISC microprocessor; Electronic design automation; Scene programmable gate array; VHDL language
In the early-1980s emerged the RISC technology has been the mainstream which the computer developed, RISC microprocessor’s some elementary theories is the computer domain important basis general knowledge, but realized specifically still had the difficulty. The electronic design automation (Electronic Design Automation, is called EDA) is the modern electron design core technologies. Carries on the electronic system design using the EDA technology the essential target is completes specific IC (ASIC) the design, but scene programmable gate array (FPGA) and complex programmable logical component (CPLD) realizes this way mainstream component. The scene programmable general gate array (Field Program mableGateArray, is called FPGA) the interior has the rich programmable resources. The FPGA exterior segment are very few, the electric circuit simply, to be advantageous for the control. FPGA present has reached thousands of gates to mark (10million-gatemark), the speed may reach 200~400MHz. This article introduced one kind based on the FPGA technology 8 RISC microprocessors which (VHSICHardw are Description Language) the language realizes with VHDL, and has given the simulation comprehensive result.
Microprocessor function, composition and set of instructions
This article designs the RISC microprocessor has followed the RISC machine’s principle of equality: The instruction strip numbers few and highly effective, the command length is fixed, the addressing system does not surpass two kinds, to use the register, to raise the instruction execute speed, the instruction explanation massively to use hard on-line control and so on.
RISC microprocessor’s function and composition
The microprocessor is entire computer system’s core, it has the following basic function: Command control, work management, timing control, data smoothing. This article designs the microprocessor mainly by the controller, the logic unit and the register is composed, but also includes the program counter, the decoder and so on some other essential logical unit. The controller is issued that the order “the policy-making organ”, namely completes coordinated and the direction entire computer system’s operation. Is opposite says in the controller, the logic unit accepts controller’s order to carry on the movement, namely the logic unit carries on the complete operation is the control signal which sends out by the controller directs, therefore it is the executive component. The memory is the retaining device, the memory cell length is 8, uses for to deposit the procedure and the data.
Microprocessor’s set of instructions
Microprocessor’s command length is 16 fixed-length, each instruction accounts for two memory cells, the addressing system only has immediately the addressing, the direct addressing two kinds. This RISC microprocessor has selected use frequency high 8 kind of instruction LDA, STO, JMP, ADD, AND, XOR, SKZ, HLT and so on. The instruction operation code takes the instruction word high 4, has reserved the space, is advantageous for the later set of instructions the expansion. The instruction cycle is composed of 8 clocks, each clock must complete the fixed operation. Part typical instruction’s operation flow chart as shown in Figure 1.
Figure 1 part of instruction operation flow
Essential module design
The RISC microprocessor is a complex digital logic electric circuit, but its basic part’s logic is not complex, may divide into it clock producer, instruction register, accumulator, units and so on arithmetic logic unit, data controller, condition controller, program counter, address multiplexer to consider. When the hardware confirms also needs to establish some like ROM/RAM and the address decoder and so on essential periphery component. The following is several essential module designs.
Clock producer’s design
Figure 2 clock producer electric circuit’s design
Clock producer Pulse produces electric circuit as shown in Figure 2, computer’s synchronized action needs the time indice, it uses the succession signal to manifest, the clock producer produces these succession signal component. Figure 2 clock producer use external clock signal clk produces a series of clock signal clk1, fetch, aluclk and so on, and escorts to microprocessor’s other parts. rst is controlling microprocessor’s replacement and the starting operation, as soon as when rst enters the high level, microprocessor on conclusion present operation, so long as and rst pauses in the high level condition, microprocessor on maintenance reset state. after rst returns to the low level, is then arriving the fetch rise along starts the microprocessor to start to work.
Because in clock producer’s to microprocessor each kind of operation implementation time control, therefore its performance quality has fundamentally decided the entire microprocessor’s riding quality. This design uses the synchronized state machine’s design method, enables clk1, fetch, alu_clk to have the remarkable promotion in the jump time synchronism performance, builds the good foundation for the overall system performance’s enhancement.
Condition controller’s design
Condition controller’s circuit diagram as shown in Figure 3. From the way which realizes looked that the RISC microprocessor and the common microprocessor’s difference lies, its sequential control signal’s formation part is with the hard wired logic realizes, but uses the microprogram control. Because the component itself designs is quite complex, and has the strict request to each control signal’s succession, therefore its VHDL procedure realizes with limited state machine FSM.
Figure 3 condition controller electric circuit
The syntagma procedure is as follows:
architecturertlofstatctlis
typemystateis(st0, st1, st2, st3, st4, st5, st6, st7);
signalcurstate:mystate;
begin
process(clk1, ena)
begin
iffallingedge(clk1) then
if (ena=’0′)then
curstate<=st0; incpc<=’0′;
load_acc<=’0′; loadpc<=’0′;
rd<=’0′; wr<=’0′; loadir<=’0′;
datactlena<=’0′; halt<=’0′;
else
case curstate is
when st0 => ……
when st1 => ……
when st2 => ……
when st3 =>cur_state<=st4;
if(opcode=hlt)then ……
else ……
whenst4=>curstate<=st5;
if(opcode=jmp)then ……
elsif (opcode=addoropcode=ann
oropcode=xoooropcode=lda) then
elsif(opcode=sto)then…else…
when st5 =>curstate<=st6;
if (opcode=addoropcode=annor
opcode=xoooropcode=lda)
then ……
elsif (opcode=skzandzero=’1′)
then ……
elsif(opcode=jmp) then ……
elsif(opcode=sto) then ……
else ……
when st6 =>curstate<=st7;
if(opcode=sto)then ……
elsif (opcode=addoropcode=ann
oropcode=xoooropcode=lda)
then ……
else ……
when st7 =>curstate<=st0;
if (opcode=skzandzero=’1′)then ……
else ……
when others=> ……
endcase;
endif;
endif;
endprocess;
endrtl;
Arithmetic logic unit ALU design
ALU is the unit which the overwhelming majority instruction must pass through, all operations carry on arithmetic logic unit ALU. ALU accepts 4 instruction operation codes which instruction register IR sends, according to different instruction, ALU, in signal alu_clk is jumping along triggering under completes each kind of arithmetic logic operation. Microprocessor various cellular construction as shown in Figure 4.
The software synthesis and the simulation and the hardware realize
Microprocessor’s software synthesis and simulation
This microprocessor design altogether has 11 basic modules, besides preamble analysis 3 modules, but also has instruction register IR, accumulator ACC, program counter PC, simple memory ROM/RAM, modules and so on address multiplexer ADDR. All modules use Quartus4.2 to synthesize alone, and debugs passes, and produces has the independent *.bsf document, finally founds top document top.bdf, connects like Figure all basic module’s bsf document 4 form. After completing the top layer design, uses Quartus4.2 to carry on the synthesis and the simulation. System simulation’s partial result as shown in Figure 5, may see from Figure 5, deposits when the memory different address 2 operands 3CH(00111100) and 18H(00011000) different or, result 24H(00100100), in the signal wr rise enters in the memory along triggering remaining after deduction. We may see clearly each instruction is completes in an instruction cycle. On data bus data is recording the instruction operational aspect, simultaneously may also see when the free time it assumes the high-resistance condition.
Figure 4 microprocessor various parts’ structure
Figure 5 simulation profile
The main procedure is as follows:
Address machine code assembly language source program
00 11000000 JMP L1; L1->PC
01 00000100
04 10100000 LDA R2; (0E)->R2
05 00001110
06 10000000 XORR1, R2; (R1)xor(R2)- > (R1)
07 00001111
08 11000001 STO ; (R1)->(0F)
0A 00000000 HLT ; stop
0B 00000000
0E 00111100
0F 00011000
Microprocessor’s hardware realizes
Carries on based on the FPGA RISC microprocessor’s final hardware confirmation on the GW48EDA system which the Hangzhou Kang core company produces. After front simulation result confirmation unmistakable, selects GW48EDA system’s electric circuit pattern No.5, consults this system’s pin comparative table to lock various pins, afterward must translate one time, in order to translate the pin locking information the programming downloading document. Finally translates the good top.sof document to the goal component FPGA downloading, obtains satisfies the design requirements the chip. This design’s carrier selects Altera Corporation’s Cyclone series FPGA component EP1C6Q240C6, the hardware confirmation result indicated that this RISC microprocessor clock rate is 23.02MHz, its function achieves the design requirements completely.
Concluding remark
This article has had the RISC microprocessor’s basic function based on the FPGA microprocessor, moreover it easy to optimize the promotion. This microprocessor not only may take a module to use on the piece the systematic design, moreover fully had also demonstrated uses FPGA and VHDL carries on the EDA number system design the superiority, has the use value.
