Abstract: The small scale LED lattice demonstration use is widespread, uses when the monolithic integrated circuit controls, needs to expand the massive peripheral resource, and is not advantageous carries on the expansion, the revision and the maintenance. Has in the system programmable logic component is rich the I/O mouth and the internal resources, component’s programming and the revision also great convenience. In this article, uses in system programmable logic component EPM7128 realizes as the core to the LED lattice demonstration control, not only simplified the peripheral circuit, moreover easy to revise, the expansion and the maintenance.
Key word: The programmable logical component, is programmable in the system, LED lattice
In the system programmable technology (ISP-In System Programming) and in the system programmable series component, is the 90s rapidly expand one kind of new technology and the new component. The scene programmable component (FPGA and CPLD) and so on ISP components do not need the programmer, provides the programming suite using the component manufacturer, uses from goes against, but under modulation design method, the use schematic diagram or the hardware description language (VHDL) and so on methods describe the circuit logic relations, may to install directly on the goal board the component programming. It easy to study, Yi Yong, to simplify the system design, reduced the system scale, reduced the design cycle, reduced the production design cost, thus has brought the revolutionary change for electronic products’ design and the production.
1st, system structure and principle of work
The LED lattice display control’s traditional way is uses the monolithic integrated circuit or the system machine realizes as CPU, when the system demonstration’s information are quite many, because monolithic integrated circuit’s input/output port (I/O) limited, will select this method the cost to increase greatly, system and procedure design difficulty also sharp growth; Moreover, when after the system completes, when revises, the change display mode or the expansion, must modify the place is quite big, even has the possibility need redesign; Moreover, in demonstrated that the system in primarily, monolithic integrated circuit’s operation and the control and so on major function’s use factor is very low, monolithic integrated circuit’s superiority cannot obtain the display, is equal in is very big the resources waste. If uses the scene programmable logic component to design the controller as CPU, chooses the appropriate component, using the component rich I/O mouth, the internal logic and the segment resources, uses from goes against, but under modulation design method, may design the entire display system conveniently. Because the PLD component’s periphery component are very few, and may (be possible multiplying) to carry on using the PLD programming port in the system programs, causes system’s revision, the display mode change and the expansion changes is simple, is convenient.
This system uses the single 16×16LED lattice by a row left shift (either right lateral) demonstrated that the Chinese character or the character, must demonstrate the Chinese character or the mark 16×16 the lattice matrix already deposited in the matrix memory. The display control switch (CPLD) EPM7128SLC84-15 realizes by the complex programmable logical component, system composition functional block diagram as shown in Figure 1. The system principle is the PLD control module first produces the lattice matrix address, and deposits from the memory readout in 16 registers, then outputs the LED lattice the row, simultaneously syzygy array scan round by dynamic demonstration data, when needs to demonstrate that the data matrix the row and the row which selects can the sychromesh, may demonstrate the Chinese character or the mark correctly.
Figure 1 lattice display control switch functional block diagram
2nd, controller design and principle of work
May see from the diagram, system’s key lies in controller’s design. The LED lattice demonstrated that the data address the production, the spot array scanning and must demonstrate the data the coordination as well as the lattice display mode control realizes must realize by the controller. Carries on the design to the single 16×16LED lattice display control switch top layer logic schematic diagram as shown in Figure 2.
Figure 2 controller top layer electric circuit schematic diagram
In the schematic diagram contains 5 modules, the sequ module produces reads the address coordination which signal RDN and 10 address wires (AD [9..0]) most low address AD0, AD0 and other modules produce, (DATA [7..0]) reads leaves ranks the high byte (when AD0=1) and the low byte through 8 bit data lines from the memory (when AD0=0), because 16×16 the lattice matrix data is 32 bytes, each row including two byte namely 16, it [7..0] and LOUT [7..0] constitutes by HOUT; Module add16 provides a slow clock by adclk to constitute 16 enters the system counter, its output gives the addr16 module, to change mold counter addr16 provides a mold, controls the lattice through mold’s rule change according to display modes and so on left shift or right lateral carries on the demonstration; Module decode4_16 is 4-16 decoders, it outputs ROUT [15..0] to connect the LED lattice the row, may select 16×16LED lattice some row, and demonstrates the sequ module output the lattice height byte (matrix) the data; Module addr16 is the lattice display control core, to realize the lattice Chinese character to chase a row migration to demonstrate from right to left, it mold which provides by the add16 module, constitutes two in the addr16 interior changes the mold counter, uses for to produce reads the matrix data address AD [4..1], other produces 16×16LED array scanning select address SUABAD [3..0], arranges in order the scanning select address after the decode4_16 decoding outputs; Module addr1 is the character choice counter, its output may control many LED monitor’s demonstration and the display mode.
Control nucleus module addr16 uses the AHDL language design, in development software MAX plus Ⅱin 10.2 realizes, the procedure as follows shows.
SUBDESIGN addr16
(
ckdsp, reset, in [3..0]: INPUT;
ad [4..1], subad [3..0]: OUTPUT;
)
VARIABLE
reg1 [3..0]: DFF;
reg2 [3..0]: DFF;
reg3 [3..0]: DFF;
BEGIN
reg1[].clk=ckdsp;
reg1[].clrn=reset;
reg2[].clk=ckdsp;
reg2[].clrn=reset;
reg3[].clk=! ckdsp;
reg3[].clrn=reset;
reg2[].d=15-in[];
if reg1[].q>=in[] then
reg1[].d=0;
else
reg1[].d=reg1[].q 1;
end if;
ad[]=reg1[];
reg3[].d=reg1[].q reg2[].q;
subad[]=reg3[].q;
END;
In order to realize the character to chase a row migration to demonstrate from right to left, module addr16 internal design two changed the mold addition counters by the add16 control, an output was ad [4..1] (4 address wires), another output was subad [3..0] (row scanning pilot wire). May see from the procedure, when the mold inputs in [3..0] =0, ad [4..1] =0, but subad [3..0] =15, this time ad [9..5] are also equal to zero, AD0 changes in 0 and 1, namely reads out the first character the first row and demonstrates in the LED 16th row; When the mold inputs in [3..0] =1, under register pulse AD0 function, ad [4..1] and subad [3..0] for binary addition counter, but ad [4..1] from 0 add to 1 returns to 0, simultaneously subad [3..0] from 14 add to 15 returns to 14, this time ad [9..5] were still equal to zero, AD0 changes in 0 and 1, namely reads out the first character first, second row and demonstrates in the LED 15th, 16 rows…From this analogy, when obviously the module add16 addition register output from 0 changes to 15, the LED lattice character will chase the row motion demonstration from left to right. Above procedure in MAX plusⅡ10.2 on simulation confirmation result as shown in Figure 3. By the simulation result may see that by counts the digital-analog control to input two which in [3..0] control changes the mold counter outputs ad [4..1] and subad [3..0] the result correctly unmistakable.
Figure 3 addr16 module simulation succession chart
In the design, should pay attention to module sequ the register clock CLK frequency choice to be bigger than module add16 the register clock adclk frequency, the addr16 register clock for address most low position AD0, the character choice counter clock pulse is by far 16 enters system module add16 highest order OUT3. Thus, ad [4..1] and subad [3..0] synchronized change enough quick, may see the complete character on lattice LED, and, when add16 registers to 15 produces carrying returns to 0, character choice module addr1 obtains a register pulse and adds 1 (rise along triggering), hereafter demonstration next character.
3rd, system expansion
Above for demonstration single character system, if simultaneously demonstrated when many characters, may defer to Figure 1 to join in the dashed line frame the part, and module addr1 designs addr16 the form, takes addr1 AD4 the register pulse then. According to the EPM7128SLC84-15 resources (64 I/O mouths, 2 overall situation clocks, 1 overall situation replacement and 5 may multiplying private port, 5000 equivalent logical gates, 192 internal registers), if the exterior expansion decoder, may not control effectively restricts 16 characters the demonstrations; But uses time the exterior decoder, may control the character number will increase greatly, only want pays attention to clock CLK the frequency to need to enhance, cannot see by the vision the entire character the twinkle is a datum.
4th, conclusion
Above lattice character display system in development software MAX plusⅡon 10.2 is unmistakable after the simulation confirmation, and already successfully applied in the coal mine electric power supervisory system’s large screen display. Moreover, because the component includes the rich programmable segment resources, when system display mode and demonstration character integer change, only needs through the development kit to revise controller’s control logic and the connection relations, will revise the procedure which completes through to download the electric cable again to download to the component then, but the circuit wafer may not make any modification, obviously, system’s maintenance and the revision are extremely convenient and easy. Certainly, because the CLPD driving force is limited, when lattice LED demonstration brightness is insufficient, needs to increase the LED driving circuit by to obtain the appropriate LED demonstration brightness.
Reference:
1st, Song Wanjie, Luo abundant, Wu Shunjun. CPLD technology and application. Xidian University Publishing house, 1999
2nd, translations and so on Liu Bao qin, Altera programmable logic component and application. Tsinghua University publishing house, 1995
3rd, Altera programmable logic component training plan. Product construction and software. Altera,1995
4th, Altera Corporation Data Book 1998
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